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Code Activity
yosys/frontends/verilog
History
Exact
Gary Wong 5feb1a1752 verilog: add support for SystemVerilog string literals. 
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-07-03 20:51:12 -06:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
const2ast.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
Makefile.inc Treat all bison warnings as errors in verilog front-end 2020-07-15 11:57:31 +02:00
preproc.cc set default_nettype to wire for resetall 2022-08-10 13:28:19 +02:00
preproc.h verilog: save and restore overwritten macro arguments 2021-07-28 21:52:16 -04:00
verilog_frontend.cc Update verilog_frontend.cc 2025-05-08 10:37:04 +12:00
verilog_frontend.h verilog: Squash a memory leak. 2021-06-14 17:07:41 +02:00
verilog_lexer.l verilog: add support for SystemVerilog string literals. 2025-07-03 20:51:12 -06:00
verilog_parser.y verilog: fix parser "if" memory errors. 2025-06-22 23:57:42 -04:00