289 commits

Author	SHA1	Message	Date
Clifford Wolf	8263f6a74a	Fixed win32 troubles with f.readsome()	2014-10-11 11:36:22 +02:00
Clifford Wolf	51b1824979	Disabled "cover -d" on win32	2014-10-11 10:49:43 +02:00
Clifford Wolf	ee5165c6e4	Moved patmatch() to yosys.cc	2014-10-10 18:20:17 +02:00
Clifford Wolf	774933a0d8	Replaced fnmatch() with patmatch()	2014-10-10 18:02:17 +02:00
Clifford Wolf	bbd808072b	Added format __attribute__ to stringf()	2014-10-10 17:22:08 +02:00
Clifford Wolf	4569a747f8	Renamed SIZE() to GetSize() because of name collision on Win32	2014-10-10 17:07:24 +02:00
Clifford Wolf	9dea161321	sort cell types in "stat" output by name	2014-10-03 19:21:04 +02:00
Clifford Wolf	f9a307a50b	namespace Yosys	2014-09-27 16:17:53 +02:00
Clifford Wolf	f7bb8f244b	Alphabetically sort port names in "show" output	2014-09-19 11:13:10 +02:00
Ruben Undheim	79cbf9067c	Corrected spelling mistakes found by lintian	2014-09-06 08:47:06 +02:00
Clifford Wolf	8927aa6148	Removed $bu0 cell type	2014-09-04 02:07:52 +02:00
Clifford Wolf	37fe7c7bdf	Removed references to yosys-svgviewer from docs	2014-09-02 04:03:06 +02:00
Clifford Wolf	9f00a0cd2d	Using "xdot" instead of "yosys-svgviewer" in show command	2014-09-02 03:28:46 +02:00
Clifford Wolf	d5148f2e01	Moved "share" and "wreduce" to passes/opt/	2014-09-01 11:45:26 +02:00
Clifford Wolf	084685f480	Implemented "rename -enumerate -pattern"	2014-08-26 12:51:08 +02:00
Clifford Wolf	19cff41eb4	Changed frontend-api from FILE to std::istream	2014-08-23 15:03:55 +02:00
Clifford Wolf	fff12c719f	Added "stat -width"	2014-08-22 17:20:28 +02:00
Clifford Wolf	98442e019d	Added emscripten (emcc) support to build system and some build fixes	2014-08-22 16:20:22 +02:00
Clifford Wolf	a3494fa9ed	Added "plugin" command	2014-08-22 14:00:11 +02:00
Clifford Wolf	7f734ecc09	Added module->uniquify()	2014-08-16 23:50:36 +02:00
Clifford Wolf	13f2f36884	RIP $safe_pmux	2014-08-14 11:39:46 +02:00
Clifford Wolf	0b8b8d41eb	Fixed build with gcc-4.6	2014-08-07 22:37:01 +02:00
Clifford Wolf	2501abe1ee	Various fixes and improvements in wreduce pass	2014-08-05 19:01:41 +02:00
Clifford Wolf	5b3dc07b9a	Removed old "constmap" from wreduce code	2014-08-05 16:53:53 +02:00
Clifford Wolf	523df73145	Added support for truncating of wires to wreduce pass	2014-08-05 14:47:03 +02:00
Clifford Wolf	d3b1a29708	Cleanups and improvements in wreduce pass	2014-08-05 13:11:04 +02:00
Clifford Wolf	1c182cedb7	Added mux support to wreduce command	2014-08-05 12:49:53 +02:00
Clifford Wolf	0bb6942218	Added "show -signed"	2014-08-04 15:40:08 +02:00
Clifford Wolf	ebbbe7fc83	Added RTLIL::IdString::in(...)	2014-08-04 15:40:07 +02:00
Clifford Wolf	027376515a	Progress in "wreduce" pass	2014-08-03 20:02:42 +02:00
Clifford Wolf	0b02f6ca30	Added "wreduce" command (work in progress)	2014-08-03 15:02:05 +02:00
Clifford Wolf	9bb5298c10	Fixes in show command (related to new IdString)	2014-08-03 12:40:23 +02:00
Clifford Wolf	04727c7e0f	No implicit conversion from IdString to anything else	2014-08-02 18:58:40 +02:00
Clifford Wolf	768eb846c4	More bugfixes related to new RTLIL::IdString	2014-08-02 18:14:21 +02:00
Clifford Wolf	b9bd22b8c8	More cleanups related to RTLIL::IdString usage	2014-08-02 13:19:57 +02:00
Clifford Wolf	14412e6c95	Preparations for RTLIL::IdString redesign: cleanup of existing code	2014-08-02 00:45:25 +02:00
Clifford Wolf	d13eb7e099	Added ModIndex helper class, some changes to RTLIL::Monitor	2014-08-01 17:14:32 +02:00
Clifford Wolf	cdae8abe16	Renamed port access function on RTLIL::Cell, added param access functions	2014-07-31 16:38:54 +02:00
Clifford Wolf	b5a9e51b96	Added "trace" command	2014-07-31 15:02:16 +02:00
Clifford Wolf	e6d33513a5	Added module->design and cell->module, wire->module pointers	2014-07-31 14:11:39 +02:00
Clifford Wolf	1cb25c05b3	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	2014-07-31 13:19:47 +02:00
Clifford Wolf	6400ae3648	Added write_file command	2014-07-30 19:59:29 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	10e5791c5e	Refactoring: Renamed RTLIL::Design::modules to modules_	2014-07-27 11:18:30 +02:00
Clifford Wolf	4c4b602156	Refactoring: Renamed RTLIL::Module::cells to cells_	2014-07-27 01:51:45 +02:00
Clifford Wolf	f9946232ad	Refactoring: Renamed RTLIL::Module::wires to wires_	2014-07-27 01:49:51 +02:00
Clifford Wolf	d68c993ed2	Changed more code to the new RTLIL::Wire constructors	2014-07-26 21:30:38 +02:00
Clifford Wolf	946ddff9ce	Changed a lot of code to the new RTLIL::Wire constructors	2014-07-26 20:12:50 +02:00
Clifford Wolf	97a59851a6	Added RTLIL::Cell::has(portname)	2014-07-26 16:11:28 +02:00
Clifford Wolf	f8fdc47d33	Manual fixes for new cell connections API	2014-07-26 15:58:23 +02:00