N. Engelhardt
fcc1c14adc
error if multiple -g options are given for abc
2020-01-06 19:10:13 +01:00
N. Engelhardt
7764b62d23
check scratchpad for arguments in abc pass too
2020-01-06 10:46:44 +01:00
N. Engelhardt
b376548fb9
inherit default values when checking scratchpad for arguments
2020-01-06 10:46:10 +01:00
N. Engelhardt
b2ad781b07
share codepath for scratchpad argument handling with command arguments
2020-01-03 14:11:41 +01:00
N. Engelhardt
341fd872b5
Merge branch 'master' of https://github.com/YosysHQ/yosys into abc_scratchpad_script
2020-01-03 12:28:48 +01:00
Eddie Hung
d6242be802
Merge pull request #1601 from YosysHQ/eddie/synth_retime
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"abc -dff" to no longer retime by default
2020-01-02 08:46:24 -08:00
Miodrag Milanovic
e0c879684f
take skip wire bits into account
2020-01-01 16:13:14 +01:00
Eddie Hung
22fe931c86
Grammar
2019-12-30 15:07:15 -08:00
Eddie Hung
566d9fb77f
Revert "ABC to call retime all the time"
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This reverts commit 9aa94370a5
2019-12-30 13:28:29 -08:00
Marcin Kościelnicki
a24596def3
iopadmap: Emit tristate buffers with const OE for some edge cases.
2019-12-25 17:37:58 +01:00
Eddie Hung
3b559de6e9
Interpret "abc9 -lut" as lut string only if [0-9:]
2019-12-18 12:21:12 -08:00
N. Engelhardt
c8bc1793a4
check scratchpad variable abc9.scriptfile
2019-12-17 19:39:55 +01:00
N. Engelhardt
91f427d719
check scratchpad variables for custom abc scripts
2019-12-13 12:54:52 +01:00
Marcin Kościelnicki
2abe38e73e
iopadmap: Refactor and fix tristate buffer mapping. ( #1527 )
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The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
2019-12-04 08:44:08 +01:00
David Shah
e9ce4e658b
abc9: Fix breaking of SCCs
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Signed-off-by: David Shah <dave@ds0.me>
2019-12-01 20:44:56 +00:00
Marcin Kościelnicki
6cdea425b8
clkbufmap: Add support for inverters in clock path.
2019-11-25 20:40:39 +01:00
Marcin Kościelnicki
38e72d6e13
Fix #1496 .
2019-11-18 04:16:48 +01:00
whitequark
c68722818a
flowmap: when doing mincut, ensure source is always in X, not X̅.
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Fixes #1475 .
2019-11-12 00:15:43 +00:00
whitequark
eef32195bd
flowmap: don't break if that creates a k+2 (and larger) LUT either.
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Fixes #1405 .
2019-11-11 23:13:00 +00:00
Eddie Hung
a5ac33f230
Merge branch 'master' into eddie/abc_to_abc9
2019-10-04 17:53:20 -07:00
Eddie Hung
0acc51c3d8
Add temporary abc9 -nomfs and use for synth_xilinx -abc9
2019-10-04 17:35:43 -07:00
Eddie Hung
aae2b9fd9c
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
Clifford Wolf
0e05424885
Merge pull request #1422 from YosysHQ/eddie/aigmap_select
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Add -select option to aigmap
2019-10-03 11:54:04 +02:00
Eddie Hung
265a655ef9
Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf
2019-10-02 12:43:35 -07:00
Eddie Hung
edc3780723
techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias
2019-09-30 17:20:12 -07:00
Eddie Hung
f2f19df2d4
Add -select option to aigmap
2019-09-30 15:26:29 -07:00
Miodrag Milanović
0d27ffd4e6
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in
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Open aig frontend as binary file
2019-09-30 17:49:23 +02:00
Eddie Hung
8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp
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DSP inference for Xilinx (improved for ice40, initial support for ecp5)
2019-09-29 11:26:22 -07:00
Miodrag Milanovic
3f70c1fd26
Open aig frontend as binary file
2019-09-29 13:22:11 +02:00
Marcin Kościelnicki
fd0e3a2c43
Fix _TECHMAP_REMOVEINIT_ handling.
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Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.
Fixes the problem identified in #1396 .
2019-09-27 18:34:12 +02:00
Eddie Hung
44374b1b2b
"abc_padding" attr for blackbox outputs that were padded, remove them later
2019-09-23 21:58:40 -07:00
Eddie Hung
ec08a031b5
Revert abc9.cc
2019-09-20 17:52:23 -07:00
Eddie Hung
72ce06909e
Trim mismatched connection to be same (smallest) size
2019-09-20 17:51:36 -07:00
Eddie Hung
567e5f0aa7
Fix first testcase in #1391
2019-09-20 17:51:27 -07:00
Clifford Wolf
b76fac3ac3
Add techmap_autopurge attribute, fixes #1381
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-19 20:00:52 +02:00
Marcin Kościelnicki
c9f9518de4
Added extractinv pass
2019-09-19 04:02:48 +02:00
Eddie Hung
9a73adde50
Explicitly order function arguments
2019-09-13 16:18:05 -07:00
Marcin Kościelnicki
f72765090c
Add -match-init option to dff2dffs.
2019-09-11 19:38:20 +02:00
Marcin Kościelnicki
a82e8df7d3
techmap: Add support for extracting init values of ports
2019-09-07 16:30:43 +02:00
Eddie Hung
903cd58acf
Merge pull request #1312 from YosysHQ/xaig_arrival
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Allow arrival times of sequential outputs to be specified to abc9
2019-09-05 12:00:23 -07:00
Clifford Wolf
30f1ac7ce9
Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes #1220
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-05 13:51:53 +02:00
Clifford Wolf
694a8f75cf
Add flatten handling of pre-existing wires as created by interfaces, fixes #1145
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-05 13:30:58 +02:00
Eddie Hung
c7f1ccbcb0
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-30 12:28:35 -07:00
Eddie Hung
999fb33fd0
Merge pull request #1340 from YosysHQ/eddie/abc_no_clean
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abc9 to not call "clean" at end of run (often called outside)
2019-08-30 12:27:09 -07:00
Eddie Hung
f0fef90e9d
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-30 10:30:46 -07:00
Eddie Hung
6e475484b2
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-30 09:37:32 -07:00
Eddie Hung
18cabe9370
Output has priority over input when stitching in abc9
2019-08-29 17:24:03 -07:00
Eddie Hung
3e0f73c3df
abc9 to not call "clean" at end of run (often called outside)
2019-08-29 12:12:59 -07:00
Eddie Hung
1467761060
Fix typo that's gone unnoticed for 5 months!?!
2019-08-29 10:33:28 -07:00
Eddie Hung
c4e5310823
Use a dummy box file if none specified
2019-08-28 20:58:55 -07:00
