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Code Activity
12905 commits 122 branches 59 tags 72 MiB
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172 commits

Author SHA1 Message Date
Clifford Wolf
721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Marcus Comstedt
e22e4d59b8 Made the expansion order of hierarchy deterministic 2016-05-22 16:41:26 +02:00
Clifford Wolf
0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf
043fa0fad0 Cleanup abstract modules at end of "hierarchy -top" 2016-03-21 16:37:35 +01:00
Clifford Wolf
d00c63c927 Added "submod -copy" 2016-01-08 09:08:12 +01:00
Clifford Wolf
1ec6429bad Added "singleton" pass 2015-11-07 19:10:43 +01:00
Clifford Wolf
207736b4ee Import more std:: stuff into Yosys namespace 2015-10-25 19:30:49 +01:00
Clifford Wolf
84bf862f7c Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
Clifford Wolf
2397078485 Keep modules with $assume (like $assert) 2015-07-25 12:09:57 +02:00
Clifford Wolf
6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf
c52a4cdeed Added "dffinit", Support for initialized Xilinx DFF 2015-04-04 19:00:15 +02:00
Clifford Wolf
4b44907619 documentation improvements 2015-03-29 20:22:08 +02:00
Clifford Wolf
aed4d763cf Added hierarchy -auto-top 2015-03-18 08:33:40 +01:00
Clifford Wolf
ed15400fc6 Fixed bug in "hierarchy" for parametric designs 2015-03-04 15:52:34 +01:00
Clifford Wolf
a54c994e2b Cosmetic fixes in "hierarchy" for blackbox modules 2015-02-15 12:57:41 +01:00
Clifford Wolf
0648e2874c Fixed pattern matching in "hierarchy -generate" 2015-01-04 11:45:39 +01:00
Clifford Wolf
a6c96b986b Added Yosys::{dict,nodict,vector} container types 2014-12-26 10:53:21 +01:00
Clifford Wolf
b6a7e21d2e Fixed off-by-one bug in "hierarchy -check" for positional module args 2014-12-24 16:26:18 +01:00
Clifford Wolf
bacd3699b3 Checking existence of ports in "hierarchy -check" 2014-12-19 18:47:19 +01:00
Clifford Wolf
51cfcd8331 Fixed bug in "hierarchy -top" with array of instances 2014-11-27 12:47:33 +01:00
Clifford Wolf
fe829bdbdc Added log_warning() API 2014-11-09 10:44:23 +01:00
Clifford Wolf
468ae92374 Various win32 / vs build fixes 2014-10-17 14:01:47 +02:00
William Speirs
31267a1ae8 Header changes so it will compile on VS 2014-10-17 11:41:36 +02:00
Clifford Wolf
35fbc0b35f Do not the 'z' modifier in format string (another win32 fix) 2014-10-11 11:42:08 +02:00
Clifford Wolf
ee5165c6e4 Moved patmatch() to yosys.cc 2014-10-10 18:20:17 +02:00
Clifford Wolf
774933a0d8 Replaced fnmatch() with patmatch() 2014-10-10 18:02:17 +02:00
Clifford Wolf
2ee03f5da4 set "keep" on modules with $assert cells in "hierarchy" 2014-09-30 19:16:40 +02:00
Clifford Wolf
f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Ruben Undheim
79cbf9067c Corrected spelling mistakes found by lintian 2014-09-06 08:47:06 +02:00
Clifford Wolf
1bf7a18fec Added module->ports 2014-08-14 16:22:52 +02:00
Clifford Wolf
768eb846c4 More bugfixes related to new RTLIL::IdString 2014-08-02 18:14:21 +02:00
Clifford Wolf
b9bd22b8c8 More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
Clifford Wolf
cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf
e6d33513a5 Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
Clifford Wolf
77e2d39cd0 Allow "hierarchy -generate" for $__ cells 2014-07-29 16:35:13 +02:00
Clifford Wolf
7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf
10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf
4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf
f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf
946ddff9ce Changed a lot of code to the new RTLIL::Wire constructors 2014-07-26 20:12:50 +02:00
Clifford Wolf
f8fdc47d33 Manual fixes for new cell connections API 2014-07-26 15:58:23 +02:00
Clifford Wolf
b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf
cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf
4755e14e7b Added copy-constructor-like module->addCell(name, other) method 2014-07-26 00:38:44 +02:00
Clifford Wolf
2bec47a404 Use only module->addCell() and module->remove() to create and delete cells 2014-07-25 17:56:19 +02:00
Clifford Wolf
4e802eb7f6 Fixed all users of SigSpec::chunks_rw() and removed it 2014-07-23 15:36:09 +02:00
Clifford Wolf
28b3fd05fa SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() 2014-07-22 20:58:44 +02:00
Clifford Wolf
4b4048bc5f SigSpec refactoring: using the accessor functions everywhere 2014-07-22 20:39:37 +02:00
Clifford Wolf
a233762a81 SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00
Clifford Wolf
8d04ca7d22 Added call_on_selection() and call_on_module() API 2014-07-20 15:33:06 +02:00