mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 03:32:29 +00:00
Code Activity
12228 commits 122 branches 59 tags 72 MiB
Commit graph

12228 commits

This branch
This branch
All branches
Author SHA1 Message Date
Miodrag Milanović
3c0f3504c6
Merge pull request #3290 from mpasternacki/bugfix/freebsd-build 
Fix build on FreeBSD, which has no alloca.h
 2022-04-25 10:16:50 +02:00
Miodrag Milanović
a511c27eb7
Merge pull request #3289 from YosysHQ/micko/sim_improve 
Simulation improvements
 2022-04-25 10:16:25 +02:00
Maciej Pasternacki
0302e97ebc Fix build on FreeBSD, which has no alloca.h 2022-04-24 19:35:50 +02:00
Miodrag Milanovic
bbfdea2f8a Match $anyseq input if connected to public wire 2022-04-22 17:20:17 +02:00
Miodrag Milanovic
4d80bc24c7 Treat $anyseq as input from FST 2022-04-22 16:23:39 +02:00
Miodrag Milanovic
9c7deabf94 Ignore change on last edge 2022-04-22 15:24:02 +02:00
Miodrag Milanovic
33f4009bb5 Last sample from input does not represent change 2022-04-22 13:46:11 +02:00
Miodrag Milanovic
83cad82b29 latches are always set to zero 2022-04-22 12:04:05 +02:00
Miodrag Milanovic
c989adcc2d If not multiclock, output only on clock edges 2022-04-22 12:03:39 +02:00
Miodrag Milanovic
75032a565d Set init state for all wires from FST and set past 2022-04-22 11:57:39 +02:00
Miodrag Milanovic
8fa2f3b260 Fix multiclock for btor2 witness 2022-04-22 11:53:41 +02:00
Jannis Harder
c7ef0f2932 smt2: Make write port array stores conditional on nonzero write mask 2022-04-20 17:49:48 +02:00
github-actions[bot]
29c0a59589 Bump version 2022-04-19 00:14:02 +00:00
Miodrag Milanović
c3a3f68b4d
Merge pull request #3280 from YosysHQ/micko/fix_readaiw 
Fix reading aiw from other solvers
 2022-04-18 09:49:21 +02:00
Miodrag Milanovic
2610b04033 Update abc 2022-04-18 09:27:00 +02:00
Miodrag Milanovic
1cc281ca6f verific: allow memories to be inferred in loops (vhdl) 2022-04-18 09:10:28 +02:00
Miodrag Milanović
d23260d381
Merge pull request #3282 from nakengelhardt/verific_loop_rams 
verific: allow memories to be inferred in loops
 2022-04-18 09:09:36 +02:00
github-actions[bot]
36b5caf821 Bump version 2022-04-16 00:14:57 +00:00
Marcelina Kościelnicka
25ff83f0b5 memory_share: Fix up mismatched address widths. 2022-04-15 22:01:00 +02:00
Marcelina Kościelnicka
48eea3efcf opt_dff: Fix behavior on $ff with D == Q. 2022-04-15 22:00:32 +02:00
N. Engelhardt
57bc29c64a verific: allow memories to be inferred in loops 2022-04-15 15:10:48 +02:00
Miodrag Milanovic
9508bb2330 Fix reading aiw from other solvers 2022-04-15 11:45:16 +02:00
Jannis Harder
bc48500548 tribuf: -formal option: convert all to logic and detect conflicts 2022-04-12 12:46:22 +02:00
github-actions[bot]
c1646a00ac Bump version 2022-04-09 00:15:22 +00:00
Miodrag Milanović
4772bc70d0
Merge pull request #3275 from YosysHQ/micko/clk2fflogic_fix 
Use wrap_async_control_gate if ff is fine
 2022-04-08 17:38:54 +02:00
Miodrag Milanovic
868409361c Use wrap_async_control_gate if ff is fine 2022-04-08 16:30:29 +02:00
Miodrag Milanović
bd7ee79486
Merge pull request #3273 from modwizcode/fix-build 
Do not enable features that require the support of compression compiled in
 2022-04-08 10:08:05 +02:00
Aki Van Ness
1f1a403cce pass jny: flipped the defaults for the inclusion of various bits of metadata 2022-04-08 08:05:15 +02:00
Aki Van Ness
6053856f91 pass jny: ensured the cell collection is cleared between modules 2022-04-08 08:05:15 +02:00
Aki Van Ness
5a016713cc pass jny: fixed missing quotes around the type value for the cell sort 2022-04-08 08:05:15 +02:00
Aki Van Ness
2e792857e9 pass jny: fixed the backslash escape for strings 2022-04-08 08:05:15 +02:00
Aki Van Ness
cae5ea8337 pass jny: removed the invalid json escapes 2022-04-08 08:05:15 +02:00
Aki Van Ness
dccc89e8b3 pass jny: added some todo comments about things that need to be done before a proper merge, but it should be enough for the PoC at the moment 2022-04-08 08:05:15 +02:00
Aki Van Ness
1be9bef28b pass jny: changed the constructor initializers to use parens rather than curly-braces to hopefully make GCC 4.8 happy 2022-04-08 08:05:15 +02:00
Aki Van Ness
43b2fc5566 pass jny: fixed the string escape method to be less jank and more proper 2022-04-08 08:05:15 +02:00
Aki Van Ness
52ea944012 pass jny: fixed the signed output for param value output 2022-04-08 08:05:15 +02:00
Aki Van Ness
58e2870261 pass jny: added connection output 2022-04-08 08:05:15 +02:00
Aki Van Ness
167206f2f5 pass jny: added filter options for including connections, attributes, and properties 2022-04-08 08:05:15 +02:00
Aki Van Ness
587f31b9a3 pass jny: large chunk of refactoring to make the JSON output more pretty and the internals less of a spaghetti nightmare 2022-04-08 08:05:15 +02:00
Aki Van Ness
0e20619189 metadata -> jny: migrated to the proper name for the pass 2022-04-08 08:05:15 +02:00
Aki Van Ness
bdf14557ca pass metadata: added the machinery to write param and attributes 2022-04-08 08:05:15 +02:00
Aki Van Ness
1876ed21e7 pass metadata: removed superfluous stringf calls 2022-04-08 08:05:15 +02:00
Aki Van Ness
ca03fbdc6d pass metadata: some more rough work on dumping the parameters and attributes 2022-04-08 08:05:15 +02:00
Aki Van Ness
6a90b42c48 pass metadata: fixed the MetadataWriter object initializer so GCC 4.8 is happy 2022-04-08 08:05:15 +02:00
Aki Van Ness
7a275567df pass metadata: added the output of parameters, 
it's kinda dumb at the moment and needs parsing based on type but it's a start
 2022-04-08 08:05:15 +02:00
Aki Van Ness
d8b85e1247 pass metadata: fixed some of the output formatting 2022-04-08 08:05:15 +02:00
Aki Van Ness
f6bb238051 pass metadata: initial commit of the metadata pass for exporting design metadata for yosys assisted tooling 2022-04-08 08:05:15 +02:00
Iris Johnson
ccc6060f52 Makefile: properly conditionalize features requiring compression. 2022-04-07 20:07:44 -05:00
github-actions[bot]
e0ba324236 Bump version 2022-04-08 00:15:41 +00:00
Catherine
8a1d531b25
Merge pull request #3269 from YosysHQ/micko/fix_autotop 
Reorder steps in -auto-top to fix synth command, fixes #3261
 2022-04-07 22:40:35 +00:00