* `misc/__init__.py`:
* checks if there's a `yosys-abc` in the same directory - if yes, sets the variable `sys._pyosys_abc`
* checks if there's a `share` in the same directory - if yes, sets the variable `sys._pyosys_share_dirname`
* `yosys.cc::init_share_dirname`: check for `sys._pyosys_share_dirname`, use it at the highest priority if Python is enabled
* `yosys.cc::init_abc_executable_name`: check for `sys._pyosys_abc`, use it at at the highest priority if Python is enabled
* `Makefile`: add new target, `share`, to only create the extra targets
* `setup.py`: compile libyosys.so, yosys-abc and share, and copy them all as part of the pyosys build
* `test/arch/ecp5/add_sub.py`: ported `add_sub.ys` to Python to act as a test for the share directory and abc with Python wheels, used in CI
* Created `setup.py`: Python package manifest to build `pyosys` wheels with a custom extension to build and include `libyosys.so` using Make
* `.gitignore`: Added byproducts of the Python wheel build process
* `Makefile`: Added `-undefined dynamic_lookup` to `libyosys.so` so missing symbols can be resolved by importing into a Python interpreter
* `kernel/yosys.cc`: Gated `PyImport_AppendInittab` with `!Py_IsInitialized`; as of Python 3.12, the interpreter is already initialized and `PyImport_AppendInittab` would cause an exception to be raised
* Created `wheels.yml`: CI workflow for building wheels for CPython on:
* Linux (glibc, musl) and Darwin
* x86-64 and arm64
Add `$(TARGETS)` for gen_examples and gen_images since they need the `yosys` executable.
Add guidelines source files as a prerequisite to docs/source/generated while we're at it.
It adds `DriveBit`, `DriveChunk` and `DriveSpec` types which are similar
to `SigBit`, `SigChunk` and `SigSpec` but can also directly represent
cell ports, undriven bits and multiple drivers. For indexing an RTLIL
module and for querying signal drivers it comes with a `DriverMap` type
which is somewhat similar to a `SigMap` but is guaranteed to produce
signal drivers as returned representatives.
A `DriverMap` can also optionally preserve connections via intermediate
wires (e.g. querying the driver of a cell input port will return a
connected intermediate wire, querying the driver of that wire will
return the cell output port that's driving the wire).
_What are the reasons/motivation for this change?_
abc builds unconditional because `check-git-abc` is a phony prerequisite and therefore always runs, and since it always runs it will always trigger abc to rebuild.
_Explain how this is achieved._
Convert `check-git-abc` to an order-only prerequisite. It still runs as before, but no longer triggers yosys-abc to rebuild when it does.
_If applicable, please suggest to reviewers how they can test the change._
Use rtds-action instead of yosys-cmd-ref repo.
Add rtds_action to docs configuration.
Add `.readthedocs.yaml`.
Update `DOCS_USAGE_` make target to be able to use pre-generated executables without forcing a remake.
Since 0.41, when building docs with ABCEXTERNAL set, the rule for
yosys-abc docs usage would attempt to build in-tree ABC.
This fix this regression by only including yosys-abc in
DOCS_USAGE_STDERR when ABCEXTERNAL is not set.
Signed-off-by: Mary Guillemard <mary@mary.zone>
Limit compilers to oldest and newest.
Oldest compilers test with minimum supported standard.
Newest compilers test with minimum *and* maximum supported standard.
This adjusts the way the headers kernel/{yosys,rtlil,register,log}.h
include each other to avoid the need of including headers outside of
include guards as well as avoiding the inclusion of rtlil.h in the
middle of yosys.h with rtlil.h depending on the prefix of yosys.h, and
the suffix of yosys.h depending on rtlil.h.
To do this I moved some of the declaration in yosys.h into a new header
yosys_common.h. I'm not sure if that is strictly necessary.
Including any of these files still results in the declarations of all
these headers being included, so this shouldn't be a breaking change for
any passes or external plugins.
My main motivation for this is that ccls's (clang based language server)
include guard handling gets confused by the previous way the includes
were done. It often ends up treating the include guard as a generic
disabled preprocessor conditional, breaking navigation and highlighting
for the core RTLIL data structures.
Additionally I think avoiding cyclic includes in the middle of header
files that depend on includes being outside of include guards will also
be less confusing for developers reading the code, not only for tools
like ccls.