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Code Activity
6439 commits 122 branches 59 tags 72 MiB
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216 commits

Author SHA1 Message Date
Clifford Wolf
7d3a3a3173 Added first help messages for cell types 2015-10-14 16:27:42 +02:00
Clifford Wolf
924d9d6e86 Added read-enable to memory model 2015-09-25 12:23:11 +02:00
Clifford Wolf
d5b1a90b33 Added $tribuf and $_TBUF_ sim models 2015-08-16 13:05:32 +02:00
Clifford Wolf
ff50bc2ac3 Added $tribuf and $_TBUF_ cell types 2015-08-16 12:54:52 +02:00
Larry Doolittle
6c00704a5e Another block of spelling fixes 
Smaller this time
 2015-08-14 23:27:05 +02:00
Clifford Wolf
e4ef000b70 Adjust makefiles to work with out-of-tree builds 
This is based on work done by Larry Doolittle
 2015-08-12 15:04:44 +02:00
Clifford Wolf
8d6d5c30d9 Added WORDS parameter to $meminit 2015-07-31 10:40:09 +02:00
Clifford Wolf
f0c9a099d2 Added "synth -nofsm" 2015-07-02 15:25:38 +02:00
Clifford Wolf
6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf
ed128b82d7 Added "synth -nordff -noalumacc" 2015-06-15 17:07:40 +02:00
Clifford Wolf
794d22969d Added simplemap $lut support 2015-04-27 10:16:07 +02:00
Clifford Wolf
95944eb69e make all vector-size related integer params in $mem sim model signed 
this fixes iverilog crashes such as the following:
warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647
draw_net_input.c:711: Error: malloc() ran out of memory.
 2015-04-05 17:26:53 +02:00
Clifford Wolf
706631225e Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types 2015-04-05 09:45:14 +02:00
Clifford Wolf
b005eedf36 Added $assume cell type 2015-02-26 18:04:10 +01:00
Clifford Wolf
4d34d031f9 Added "stat" to "synth" and "synth_xilinx" 2015-02-15 13:25:15 +01:00
Clifford Wolf
881dcd8af9 Added final checks to "synth" and "synth_xilinx" 2015-02-15 13:00:00 +01:00
Clifford Wolf
ec05242c27 Smaller default parameters in $mem simlib model 2015-02-15 00:20:05 +01:00
Clifford Wolf
dcf2e24240 Added $meminit support to "memory" command 2015-02-14 12:55:03 +01:00
Clifford Wolf
910556560f Added $meminit cell type 2015-02-14 10:23:03 +01:00
Clifford Wolf
04cb947d6a Added "check" command 2015-02-13 14:34:51 +01:00
Clifford Wolf
d58c3eca3a Some test related fixes 
(incl. removal of three bad test cases)
 2015-02-12 17:45:44 +01:00
Clifford Wolf
1df81f92ce Added "make mklibyosys", some minor API changes 2015-02-01 13:38:46 +01:00
Clifford Wolf
bedd46338f Added "fsm -encfile" 2015-01-30 22:46:53 +01:00
Clifford Wolf
e13a45ae61 Added $equiv cell type 2015-01-19 11:55:05 +01:00
Clifford Wolf
3ed4e34380 Added cells.lib 2015-01-16 15:50:42 +01:00
Clifford Wolf
1d96277f5d Added add_share_file Makefile macro 2015-01-08 00:23:18 +01:00
Clifford Wolf
a7e43ae3d9 Progress in memory_bram 2015-01-03 10:57:01 +01:00
Clifford Wolf
90f4017703 Added proper clkpol support to memory_bram 2015-01-02 22:57:08 +01:00
Clifford Wolf
474831643c New $mem simlib model 2015-01-02 17:11:31 +01:00
Clifford Wolf
ba43cf5807 Fixed simlib entries for $memrd and $memwr 2014-12-30 13:33:29 +01:00
Clifford Wolf
c64b1de11d Fixed build with SMALL=1 2014-12-30 11:41:24 +01:00
Clifford Wolf
4aa9fbbf3f Improvements in simplemap api, added $ne $nex $eq $eqx support 2014-12-24 10:49:24 +01:00
Clifford Wolf
72f500c950 Removed UTF-8 chars from techmap.v 2014-12-12 12:44:16 +01:00
Clifford Wolf
f1764b4fe9 Added $dffe cell type 2014-12-08 10:50:19 +01:00
Clifford Wolf
fad9cec47b Added $_DFFE_??_ cell types 2014-12-08 10:43:38 +01:00
Clifford Wolf
74ef92b9c8 Added "abc" label in synth script 2014-10-31 03:46:27 +01:00
Clifford Wolf
ab28491f27 Added "opt -full" alias for all more aggressive optimizations 2014-10-31 03:36:51 +01:00
Clifford Wolf
c3e779a65f Added $_BUF_ cell type 2014-10-03 10:12:28 +02:00
Clifford Wolf
f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf
4888d61c65 Improvements in "synth" script 2014-09-18 12:57:55 +02:00
Clifford Wolf
6644e27cd4 Fixed $macc simlib model for zero-config 2014-09-16 08:19:35 +02:00
Clifford Wolf
7815f81c32 Added "synth" command 2014-09-14 16:09:06 +02:00
Clifford Wolf
923bbbeaf0 Using alumacc in techmap.v 2014-09-14 14:50:15 +02:00
Clifford Wolf
44b5bd4b63 Fixed simlib $macc model for xilinx xsim 2014-09-08 17:09:39 +02:00
Clifford Wolf
fcb46138ce Simplified $fa undef model 2014-09-08 16:59:39 +02:00
Clifford Wolf
6dc07eb1f2 Fixes and cleanups for blackbox.v 2014-09-08 13:31:04 +02:00
Clifford Wolf
af0c8873bb Added $lcu cell type 2014-09-08 13:31:04 +02:00
Clifford Wolf
d46bac3305 Added "$fa" cell type 2014-09-08 12:15:39 +02:00
Clifford Wolf
dd887cc025 Using maccmap for $macc and $mul techmap 2014-09-07 18:24:08 +02:00
Clifford Wolf
9329a76818 Various bug fixes (related to $macc model testing) 2014-09-06 20:30:46 +02:00