437 commits

Author	SHA1	Message	Date
William Speirs	6433203b39	Wrapped init in std::set constructor	2014-10-15 00:58:05 +02:00
Clifford Wolf	35fbc0b35f	Do not the 'z' modifier in format string (another win32 fix)	2014-10-11 11:42:08 +02:00
Clifford Wolf	4569a747f8	Renamed SIZE() to GetSize() because of name collision on Win32	2014-10-10 17:07:24 +02:00
Clifford Wolf	c5c7066ea6	sat encoding for exclusive $pmux ctrl inputs in "share" pass	2014-10-03 19:01:24 +02:00
Clifford Wolf	3e4b0cac8d	added resource sharing of $macc cells	2014-10-03 12:58:40 +02:00
Clifford Wolf	c3e779a65f	Added $_BUF_ cell type	2014-10-03 10:12:28 +02:00
Clifford Wolf	600c6cb013	remove buffers in opt_clean	2014-10-03 10:04:15 +02:00
Clifford Wolf	7019bc00e4	resource sharing of $alu cells	2014-10-03 09:55:50 +02:00
Clifford Wolf	0b8cfbc6fd	Added support for "keep" on modules	2014-09-29 12:51:54 +02:00
Clifford Wolf	f9a307a50b	namespace Yosys	2014-09-27 16:17:53 +02:00
Clifford Wolf	13117bb346	Re-enabled assert for new logic loops in "share" pass	2014-09-21 19:44:08 +02:00
Clifford Wolf	96e821dc6c	Various improvements regarding logic loops in "share" results	2014-09-21 19:36:56 +02:00
Clifford Wolf	d6e2ace95b	Logic loop bugfix for "share" pass	2014-09-21 15:13:44 +02:00
Clifford Wolf	b28be0759f	Added "share -limit"	2014-09-21 15:13:06 +02:00
Clifford Wolf	a6c08b40fe	Still loop bug in "share": changed assert to warning	2014-09-21 14:51:07 +02:00
Clifford Wolf	8d60754aef	Do not introduce new logic loops in "share"	2014-09-21 13:52:39 +02:00
Clifford Wolf	edf11c635a	Assert on new logic loops in "share" pass	2014-09-21 12:57:33 +02:00
Clifford Wolf	2cbdbaad1f	Fixed wreduce $shiftx handling	2014-09-15 11:29:09 +02:00
Clifford Wolf	aab0e3bf70	Cleanup in wreduce	2014-09-14 10:01:30 +02:00
Ruben Undheim	79cbf9067c	Corrected spelling mistakes found by lintian	2014-09-06 08:47:06 +02:00
Clifford Wolf	f5a40e7043	Fixed "opt_const -fine" for $pos cells	2014-09-04 08:55:58 +02:00
Clifford Wolf	8927aa6148	Removed $bu0 cell type	2014-09-04 02:07:52 +02:00
Clifford Wolf	d5148f2e01	Moved "share" and "wreduce" to passes/opt/	2014-09-01 11:45:26 +02:00
Clifford Wolf	e07698818d	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data	2014-09-01 11:36:02 +02:00
Clifford Wolf	2a1b08aeb3	Added design->scratchpad	2014-08-30 19:37:12 +02:00
Clifford Wolf	7bbbe3580d	Optimize shift ops with constant rhs in opt_const	2014-08-24 17:08:43 +02:00
Clifford Wolf	641501203c	Added some additional log messages to opt_const	2014-08-24 17:08:43 +02:00
Clifford Wolf	410d043dd8	Renamed toposort.h to utils.h	2014-08-17 00:55:35 +02:00
Clifford Wolf	eb17fbade5	Added "opt -fast"	2014-08-16 15:34:15 +02:00
Clifford Wolf	f092b50148	Renamed $_INV_ cell type to $_NOT_	2014-08-15 14:11:40 +02:00
Clifford Wolf	ca87116449	More idstring sort_by_* helpers and fixed tpl ordering in techmap	2014-08-15 02:40:46 +02:00
Clifford Wolf	13f2f36884	RIP $safe_pmux	2014-08-14 11:39:46 +02:00
Clifford Wolf	8fd1c269ac	Fixed a performance bug in opt_reduce	2014-08-02 15:12:16 +02:00
Clifford Wolf	b9bd22b8c8	More cleanups related to RTLIL::IdString usage	2014-08-02 13:19:57 +02:00
Clifford Wolf	bd74ed7da4	Replaced sha1 implementation	2014-08-01 19:01:10 +02:00
Clifford Wolf	cdae8abe16	Renamed port access function on RTLIL::Cell, added param access functions	2014-07-31 16:38:54 +02:00
Clifford Wolf	397b00252d	Added $shift and $shiftx cell types (needed for correct part select behavior)	2014-07-29 16:35:13 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	0c86d6106c	Added SigPool::check(bit)	2014-07-27 15:38:02 +02:00
Clifford Wolf	77a1462f2d	Fixed bug in opt_clean	2014-07-27 15:13:29 +02:00
Clifford Wolf	d07a871d35	Improved performance of opt_const on large modules	2014-07-27 14:50:25 +02:00
Clifford Wolf	dbb3556e3f	Fixed a bug in opt_clean and some RTLIL API usage cleanups	2014-07-27 13:19:05 +02:00
Clifford Wolf	49f72421d5	Using new obj iterator API in a few places	2014-07-27 11:32:42 +02:00
Clifford Wolf	10e5791c5e	Refactoring: Renamed RTLIL::Design::modules to modules_	2014-07-27 11:18:30 +02:00
Clifford Wolf	4c4b602156	Refactoring: Renamed RTLIL::Module::cells to cells_	2014-07-27 01:51:45 +02:00
Clifford Wolf	f9946232ad	Refactoring: Renamed RTLIL::Module::wires to wires_	2014-07-27 01:49:51 +02:00
Clifford Wolf	946ddff9ce	Changed a lot of code to the new RTLIL::Wire constructors	2014-07-26 20:12:50 +02:00
Clifford Wolf	3f4e3ca8ad	More RTLIL::Cell API usage cleanups	2014-07-26 16:14:02 +02:00
Clifford Wolf	97a59851a6	Added RTLIL::Cell::has(portname)	2014-07-26 16:11:28 +02:00
Clifford Wolf	f8fdc47d33	Manual fixes for new cell connections API	2014-07-26 15:58:23 +02:00