3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 10:55:51 +00:00
Commit graph

4 commits

Author SHA1 Message Date
Eddie Hung
99a14b0e37 Add support for Xilinx PS7 block 2018-11-10 12:45:07 -08:00
Clifford Wolf
5f1fea08d5 Add inout ports to cells_xtra.v
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-04 11:30:55 +02:00
Tim Ansell
ad975fb694
xilinx: Adding missing inout IO port to IOBUF 2018-10-03 16:38:32 -07:00
Clifford Wolf
ff5c61b120 Added black box modules for all the 7-series design elements (as listed in ug953) 2016-03-19 11:09:10 +01:00