126 commits

Author	SHA1	Message	Date
Clifford Wolf	c38283dbd0	Small bug fixes in $not, $neg, and $shiftx models	2014-09-02 17:48:41 +02:00
Clifford Wolf	9923762461	Fixed "test_cell -simlib all"	2014-09-01 15:37:56 +02:00
Clifford Wolf	4724d94fbc	Added $alu cell type	2014-08-30 18:59:05 +02:00
Clifford Wolf	b64b38eea2	Renamed $lut ports to follow A-Y naming scheme	2014-08-15 14:18:40 +02:00
Clifford Wolf	13f2f36884	RIP $safe_pmux	2014-08-14 11:39:46 +02:00
Clifford Wolf	2145e57ef0	Bugfix in simlib.v for iverilog	2014-07-29 19:23:31 +02:00
Clifford Wolf	397b00252d	Added $shift and $shiftx cell types (needed for correct part select behavior)	2014-07-29 16:35:13 +02:00
Clifford Wolf	f1ca93a0a3	Fixed simlib.v model for $mem	2014-07-17 16:48:36 +02:00
Clifford Wolf	dcdd5c11b4	Updated simlib to new $mem/$memwr interface	2014-07-16 11:46:40 +02:00
Clifford Wolf	7370ae01e9	Added SIMLIB_NOLUT to simlib.v	2014-04-02 21:28:33 +02:00
Clifford Wolf	e24797add0	Added SIMLIB_NOSR to simlib.v	2014-04-02 21:06:55 +02:00
Clifford Wolf	d4a1b0af5b	Added support for dlatchsr cells	2014-03-31 14:14:40 +02:00
Clifford Wolf	fc3b3c4ec3	Added $slice and $concat cell types	2014-02-07 17:44:57 +01:00
Clifford Wolf	a6750b3753	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	2014-02-03 13:01:45 +01:00
Clifford Wolf	ed8ad99960	More changes to techlibs/common/simlib.v for LEC	2014-01-31 11:21:29 +01:00
Clifford Wolf	a86f33653d	Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)	2014-01-29 00:36:03 +01:00
Clifford Wolf	1e67099b77	Added $assert cell	2014-01-19 14:03:40 +01:00
Clifford Wolf	3d7a1491aa	Fixed $lut simlib model for a wider range of tools	2014-01-18 19:31:40 +01:00
Clifford Wolf	2fbaaaca7a	More changes to simlib to make it friendlier to a wider range of tools	2014-01-18 19:13:43 +01:00
Clifford Wolf	4a9e133fab	Fixed a type in $mem model in simlib.v	2014-01-18 18:54:50 +01:00
Clifford Wolf	5b96675696	Added $bu0 cell to simlib.v	2014-01-18 15:35:15 +01:00
Clifford Wolf	369bf81a70	Added support for non-const === and !== (for miter circuits)	2013-12-27 14:20:15 +01:00
Clifford Wolf	1afe6589df	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	2013-11-24 20:44:00 +01:00
Clifford Wolf	e5b974fa2a	Cleanups and bugfixes in response to new internal cell checker	2013-11-11 00:39:45 +01:00
Clifford Wolf	5998c101a4	Added $sr, $dffsr and $dlatch cell types	2013-10-18 11:56:16 +02:00
Clifford Wolf	288ba9618a	Moved common techlib files to techlibs/common	2013-09-15 11:52:57 +02:00

Renamed from techlibs/simlib.v (Browse further)