The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively
in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in
LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s.
So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost
2x resource of a LUT5.
Change the -lut parameter passed to the abc command to pass this cost
info to the ABC process.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
The MSLICEs on the Eagle series of FPGA can be configured as Distributed
RAM.
Enable to synthesis to DRAM.
As the Anlogic software suite doesn't support any 'bx to exist in the
initializtion data of DRAM, do not enable the initialization support of
the inferred DRAM.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
