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Author SHA1 Message Date
Clifford Wolf
34a7c0209d
Merge pull request #1316 from YosysHQ/eddie/fix_mem2reg 
mem2reg to preserve user attributes and src
 2019-08-22 10:24:42 +02:00
Eddie Hung
bb1a8a0190 Add test 2019-08-21 21:58:20 -07:00
Eddie Hung
d3a212ff91 opt_expr to trim A port of $shiftx if Y_WIDTH == 1 2019-08-21 21:53:55 -07:00
Eddie Hung
7d02d17b16 Reuse var 2019-08-21 19:18:40 -07:00
Eddie Hung
5c8344363f Revert "Trim shiftx_width when upper bits are 1'bx" 
This reverts commit 7e7965ca7b.
 2019-08-21 19:18:27 -07:00
Eddie Hung
c7859531c2 opt_expr to trim A port of $shiftx if Y_WIDTH == 1 2019-08-21 19:18:05 -07:00
Eddie Hung
7e7965ca7b Trim shiftx_width when upper bits are 1'bx 2019-08-21 18:43:17 -07:00
Eddie Hung
ed7be3e6b6 Add comment 2019-08-21 17:36:38 -07:00
Eddie Hung
15188033da Add variable length support to xilinx_srl 2019-08-21 17:34:40 -07:00
Eddie Hung
6d76ae4c65 Rename pattern to fixed 2019-08-21 15:46:58 -07:00
Eddie Hung
b0a3b430bf attribute -> attr 2019-08-21 15:44:07 -07:00
Eddie Hung
61b4d7ae13 Use Cell::has_keep_attribute() 2019-08-21 15:41:46 -07:00
Eddie Hung
edec73fec1 abc9 to perform new 'map_ffs' before 'map_luts' 2019-08-21 15:37:55 -07:00
Eddie Hung
6fa9e03e4c xilinx_srl to support FDRE and FDRE_1 2019-08-21 15:35:29 -07:00
Eddie Hung
3c8e8521a6 Fix polarity of EN_POL 2019-08-21 14:42:11 -07:00
whitequark
841903582f
Merge pull request #1315 from mmicko/fix_dependencies 
Fix test_pmgen deps
 2019-08-21 21:40:31 +00:00
Eddie Hung
a980f0d4be Add CLKPOL == 0 2019-08-21 14:35:40 -07:00
Eddie Hung
1c7d721558 Reject if not minlen from inside pattern matcher 2019-08-21 14:26:24 -07:00
Eddie Hung
cab2bd083e Get wire via SigBit 2019-08-21 13:47:47 -07:00
Eddie Hung
52fea5b658 Respect \keep on cells or wires 2019-08-21 13:42:03 -07:00
Eddie Hung
b808123e71 Merge branch 'eddie/fix_mem2reg' into eddie/xilinx_srl 2019-08-21 13:37:45 -07:00
Eddie Hung
a6776ee35e mem2reg to preserve user attributes and src 2019-08-21 13:36:01 -07:00
Eddie Hung
5ce0c31d0e Add init support 2019-08-21 13:05:10 -07:00
Eddie Hung
df53fe12e7 Fix spacing 2019-08-21 12:54:11 -07:00
Eddie Hung
0250712486 Initial progress on xilinx_srl 2019-08-21 12:50:49 -07:00
SergeyDegtyar
d945b8a357 Fix all comments from PR 2019-08-21 21:52:07 +03:00
Miodrag Milanovic
948b6f91a1 Fix test_pmgen deps 2019-08-21 17:00:24 +02:00
Clifford Wolf
7d8db1c053
Merge pull request #1314 from YosysHQ/eddie/fix_techmap 
techmap -max_iter to apply to each module individually
 2019-08-21 09:12:56 +02:00
SergeyDegtyar
b835ec37cb Add temp directory 2019-08-21 07:53:34 +03:00
Eddie Hung
076af2e617 Missing newline 2019-08-20 20:37:52 -07:00
Eddie Hung
9b9d759451 Fix copy-paste typo 2019-08-20 20:18:51 -07:00
Eddie Hung
fe61dcce8b Grammar 2019-08-20 20:05:51 -07:00
Eddie Hung
fce8dc7db2 Add test 2019-08-20 20:05:16 -07:00
Eddie Hung
193eae0c84 techmap -max_iter to apply to each module individually 2019-08-20 19:50:20 -07:00
Eddie Hung
33960dd3d8
Merge pull request #1209 from YosysHQ/eddie/synth_xilinx 
[WIP] synth xilinx renaming, as per #1184
 2019-08-20 12:55:26 -07:00
Eddie Hung
14c03861b6
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor 
Refactor abc9 to use port attributes, not module attributes
 2019-08-20 11:59:31 -07:00
Eddie Hung
d9fe4cccbf Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx 2019-08-20 11:57:52 -07:00
SergeyDegtyar
71dd412ac5 Fix tests; Remove simulation; 
- Add -map and -assert options for equiv_opt;
	!!! '-assert' option was commented for the next tests (unproven
$equiv cells was found):
		- dffs;
		- div_mod;
		- latches;
		- mul_pow;
- Add design -load;
- Remove simulations;
 2019-08-20 15:52:25 +03:00
Clifford Wolf
ba71e4f8f2
Merge pull request #1298 from YosysHQ/clifford/pmgen 
Improvements in pmgen
 2019-08-20 11:39:42 +02:00
Clifford Wolf
d0117d7d12
Merge branch 'master' into clifford/pmgen 2019-08-20 11:39:23 +02:00
Clifford Wolf
6ffb910d12 Add test case for real parameters 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-20 11:38:21 +02:00
Clifford Wolf
c25c1e742b
Merge pull request #1308 from jakobwenzel/real_params 
Handle real values when deriving ast modules
 2019-08-20 11:37:26 +02:00
SergeyDegtyar
153ec0541c Add new tests for ice40 architecture 2019-08-20 07:50:05 +03:00
whitequark
749ff864aa
Merge pull request #1309 from whitequark/proc_clean-fix-1268 
proc_clean: fix order of switch insertion
 2019-08-20 00:45:41 +00:00
Eddie Hung
3f4886e7a3 Fix typo 2019-08-19 10:42:00 -07:00
Eddie Hung
7e010834eb Fix typo 2019-08-19 10:41:18 -07:00
Eddie Hung
f42ba811b6 ID({A,B,Y}) -> ID::{A,B,Y} for opt_share.cc 2019-08-19 10:11:47 -07:00
Eddie Hung
29e4c8bd06 Clarify with 'only' 2019-08-19 10:00:53 -07:00
Eddie Hung
c36fca86f7 Update doc 2019-08-19 09:59:57 -07:00
Eddie Hung
d81a090d89 Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro 2019-08-19 09:56:17 -07:00