22 commits

Author	SHA1	Message	Date
Eddie Hung	f6203e6bd6	Missing endmodule	2019-09-29 21:55:53 -07:00
Eddie Hung	1123c09588	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-09-29 19:39:12 -07:00
Eddie Hung	79b6edb639	Big rework; flop info now mostly in cells_sim.v	2019-09-28 23:48:17 -07:00
Eddie Hung	8f5710c464	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-09-27 15:14:31 -07:00
Eddie Hung	93363c94a2	Oops. Actually use __NAME__ in ABC_DSP48E1 macro	2019-09-25 10:33:16 -07:00
Eddie Hung	4401e5f142	Grammar	2019-09-20 14:24:31 -07:00
Eddie Hung	e09f80479e	Fix DSP48E1 timing by breaking P path if MREG or PREG	2019-09-19 18:59:28 -07:00
Eddie Hung	362a803779	Revert "Different approach to timing" ... This reverts commit 41256f48a5.	2019-09-19 18:33:38 -07:00
Eddie Hung	41256f48a5	Different approach to timing	2019-09-19 18:33:29 -07:00
Eddie Hung	d0b202c58d	Add no MULT no DPORT config	2019-09-13 12:05:14 -07:00
Eddie Hung	247a63f55d	Add support for MULT and DPORT	2019-09-13 11:45:55 -07:00
Eddie Hung	e235dd0785	Refine diagram	2019-09-13 09:34:40 -07:00
Eddie Hung	734034a872	Add an ASCII drawing	2019-09-12 18:13:46 -07:00
Eddie Hung	c52863f147	Finish explanation	2019-09-12 18:01:49 -07:00
Eddie Hung	6bb8e6a726	Initial DSP48E1 box support	2019-09-12 17:11:01 -07:00
Eddie Hung	c26c556384	xilinx to use abc_map.v with -max_iter 1	2019-08-20 19:47:11 -07:00
Eddie Hung	f1a206ba03	Revert "Remove sequential extension" ... This reverts commit 091bf4a18b.	2019-08-20 18:17:14 -07:00
Eddie Hung	091bf4a18b	Remove sequential extension	2019-08-20 18:16:37 -07:00
Eddie Hung	e273ed5275	Wrap SRL{16,32} too	2019-08-20 15:09:38 -07:00
Eddie Hung	808f07630f	Wrap LUTRAMs in order to capture comb/seq behaviour	2019-08-20 14:49:11 -07:00
Eddie Hung	8d0cffaf20	Remove mapping rules	2019-08-20 13:11:39 -07:00
Eddie Hung	be9e4f1b67	Use abc_{map,unmap,model}.v	2019-08-20 12:39:11 -07:00

Renamed from techlibs/xilinx/abc_ff.v (Browse further)