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Author	SHA1	Message	Date
Eddie Hung	73b7ea713c	Merge pull request #1994 from YosysHQ/eddie/fix_bug1758 ... opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too	2020-05-14 11:56:22 -07:00
Eddie Hung	425867d175	logger: clean up doc	2020-05-14 10:38:31 -07:00
Eddie Hung	02df0198b6	abc9_ops: -prep_hier to create unmap module that removes Q's (* init *)	2020-05-14 10:33:57 -07:00
Eddie Hung	13f9d65b6f	abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it	2020-05-14 10:33:57 -07:00
Eddie Hung	fa31e84112	Fix broken test when ignoring abc9_flop with init == 1'b1	2020-05-14 10:33:57 -07:00
Eddie Hung	97a0a04314	abc9_ops/xaiger: further reducing Module::derive() calls by ... ... replacing _all_ (* abc9_box *) instantiations with their derived types	2020-05-14 10:33:57 -07:00
Eddie Hung	e79127fceb	Cleanup; reduce Module::derive() calls	2020-05-14 10:33:57 -07:00
Eddie Hung	cea614f5ae	ecp5: latches_map.v if *not* -asyncprld	2020-05-14 10:33:57 -07:00
Eddie Hung	fdc340db8e	ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.v	2020-05-14 10:33:57 -07:00
Eddie Hung	39759d5f0e	ecp5: fix rebase mistake	2020-05-14 10:33:57 -07:00
Eddie Hung	8d34aee3d5	abc9: update to =_$abc9_flops pattern which includes whiteboxes	2020-05-14 10:33:57 -07:00
Eddie Hung	f652a9c11c	abc9_ops: update docs	2020-05-14 10:33:57 -07:00
Eddie Hung	ca4f8c9444	xilinx: gate specify/attributes from iverilog	2020-05-14 10:33:57 -07:00
Eddie Hung	57c478c537	abc9: only do +/abc9_map if `DFF	2020-05-14 10:33:57 -07:00
Eddie Hung	2946bb60e9	abc9: rework submod -- since it won't move (* keep *) cells	2020-05-14 10:33:56 -07:00
Eddie Hung	8cda29137e	ecp5: TRELLIS_FF bypass path only in async mode	2020-05-14 10:33:56 -07:00
Eddie Hung	7146c0339e	timinginfo: ignore $specify2 cells if EN is false	2020-05-14 10:33:56 -07:00
Eddie Hung	6c34945371	xilinx/ice40/ecp5: zinit requires selected wires, so select them all	2020-05-14 10:33:56 -07:00
Eddie Hung	b65610fb62	abc9_ops: move assert	2020-05-14 10:33:56 -07:00
Eddie Hung	ed7cb0b095	abc9: put 'aigmap' back	2020-05-14 10:33:56 -07:00
Eddie Hung	a323881e15	xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells	2020-05-14 10:33:56 -07:00
Eddie Hung	b3e2538a14	abc9_ops: fix bypass boxes using (* abc9_bypass *)	2020-05-14 10:33:56 -07:00
Eddie Hung	d5a8aaba8c	abc9_ops: tidy up, suppress error if no boxes/holes	2020-05-14 10:33:56 -07:00
Eddie Hung	e2044fd9c7	abc9_ops: -prep_delays to not insert delay box if input connection is const	2020-05-14 10:33:56 -07:00
Eddie Hung	8b5fb99245	abc9_ops: cleanup; -prep_dff -> -prep_dff_submod	2020-05-14 10:33:56 -07:00
Eddie Hung	7cd3f4a79b	abc9_ops: add -prep_bypass for auto bypass boxes; refactor ... Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier	2020-05-14 10:33:56 -07:00
Eddie Hung	bb840cca9c	abc9_ops: -reintegrate to handle $_FF_; cleanup	2020-05-14 10:33:56 -07:00
Eddie Hung	e357b40e7a	xaiger: no longer use nonstandard even/odd to designate +ve/-ve polarity	2020-05-14 10:33:56 -07:00
Eddie Hung	4017cc6380	aiger: -xaiger to return $_FF_ flops	2020-05-14 10:33:56 -07:00
Eddie Hung	722540dbf9	abc9: not enough to techmap_fail on (* init=1 *), hide them using $__	2020-05-14 10:33:56 -07:00
Eddie Hung	5ad3a85288	abc9: test to use box file instead of auto	2020-05-14 10:33:56 -07:00
Eddie Hung	c50601e35e	abc9: restore selected_modules()	2020-05-14 10:33:56 -07:00
Eddie Hung	8fbb55f4ab	synth_*: no need to explicitly read +/abc9_model.v	2020-05-14 10:33:56 -07:00
Eddie Hung	63246a5c0e	Revert "Merge pull request #1917 from YosysHQ/eddie/abc9_delay_check" ... This reverts commit 759283fa65, reversing changes made to f41c7ccfff.	2020-05-14 10:33:56 -07:00
Eddie Hung	48052ad813	abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too	2020-05-14 10:33:56 -07:00
Eddie Hung	7812a2959b	kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero	2020-05-14 10:33:56 -07:00
Eddie Hung	4cec21b93e	abc9_ops: -prep_dff_map to error if async flop found	2020-05-14 10:33:56 -07:00
Eddie Hung	6c66030dfb	Uncomment negative setup times; clamp to zero for connectivity	2020-05-14 10:33:56 -07:00
Eddie Hung	c41c180f68	abc9: remove redundant wbflip	2020-05-14 10:33:56 -07:00
Eddie Hung	4c6647a469	xaiger: always sort input/output bits by port id ... redundant for normal design, but necessary for holes	2020-05-14 10:33:56 -07:00
Eddie Hung	ec4bbb1444	abc9: generate $abc9_holes design instead of <name>$holes	2020-05-14 10:33:56 -07:00
Eddie Hung	c52bb11fb6	abc9_ops: more robust	2020-05-14 10:33:56 -07:00
Eddie Hung	8d7b3c06b2	abc9: suppress warnings when no compatible + used flop boxes formed	2020-05-14 10:33:56 -07:00
Eddie Hung	cdd250ef16	xilinx: update abc9_dff tests	2020-05-14 10:33:56 -07:00
Eddie Hung	762b6ad74a	xilinx: remove no-longer-relevant test	2020-05-14 10:33:56 -07:00
Eddie Hung	6f4f795953	aiger/xaiger: use odd for negedge clk, even for posedge ... Since abc9 doesn't like negative mergeability values	2020-05-14 10:33:56 -07:00
Eddie Hung	fb447951be	abc9: cleanup	2020-05-14 10:33:56 -07:00
Eddie Hung	0d84ff3fc4	Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init" ... This reverts commit 8c702b6cc0221a00021a3e4661c883bb591c924b.	2020-05-14 10:33:56 -07:00
Eddie Hung	8bad885e78	abc9_ops: -prep_dff_map to check $_DFF_[NP]_.Q drives module output	2020-05-14 10:33:56 -07:00
Eddie Hung	489e83fc1e	abc9_ops: do away with '$abc9_cells' selection	2020-05-14 10:33:56 -07:00