3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-05-31 19:29:14 +00:00
Commit graph

7 commits

Author SHA1 Message Date
Eddie Hung
6fa9e03e4c xilinx_srl to support FDRE and FDRE_1 2019-08-21 15:35:29 -07:00
Eddie Hung
3c8e8521a6 Fix polarity of EN_POL 2019-08-21 14:42:11 -07:00
Eddie Hung
a980f0d4be Add CLKPOL == 0 2019-08-21 14:35:40 -07:00
Eddie Hung
1c7d721558 Reject if not minlen from inside pattern matcher 2019-08-21 14:26:24 -07:00
Eddie Hung
5ce0c31d0e Add init support 2019-08-21 13:05:10 -07:00
Eddie Hung
df53fe12e7 Fix spacing 2019-08-21 12:54:11 -07:00
Eddie Hung
0250712486 Initial progress on xilinx_srl 2019-08-21 12:50:49 -07:00