mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-26 09:24:37 +00:00
Code Activity
16043 commits 122 branches 59 tags 72 MiB
Commit graph

184 commits

Author SHA1 Message Date
Eddie Hung
efd04880db Add RAM32X1D support 2019-06-24 16:16:50 -07:00
Eddie Hung
d54dceb547 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-22 19:44:17 -07:00
Eddie Hung
65c022c257 Remove DFF and RAMD box info for now 2019-06-21 20:41:14 -07:00
Eddie Hung
9abde12110 Add $__XILINX_MUXF78 to preserve entire box 2019-06-21 15:47:42 -07:00
Eddie Hung
ee428f73ab Remove WIP ABC9 flop support 2019-06-14 10:37:52 -07:00
Eddie Hung
54379f9872 Disable dist RAM boxes due to comb loop 2019-06-11 12:02:51 -07:00
Eddie Hung
8a708d1fdb Remove #ifndef ABC 2019-06-11 12:02:31 -07:00
Eddie Hung
7166dbe418 Remove abc_flop attributes for now 2019-06-06 14:35:38 -07:00
Eddie Hung
6ed15b7890 Update abc attributes on FD*E_1 2019-06-05 12:33:40 -07:00
Eddie Hung
b6e59741ae Typo 2019-06-03 20:21:41 -07:00
Eddie Hung
ebcc85b9b8 Fix `ifndef 2019-06-03 12:37:02 -07:00
Eddie Hung
01f71085f2 Add FD*E_1 -> FD*E techmap rules 2019-05-31 18:11:24 -07:00
Eddie Hung
1ad33c3b5a Remove whitebox attribute from DRAMs for now 2019-05-30 13:07:29 -07:00
Eddie Hung
fdfc18be91 Carry in/out to be the last input/output for chains to be preserved 2019-05-30 01:23:36 -07:00
Eddie Hung
54e28eb3ea Re-enable lib_whitebox 2019-05-27 23:08:55 -07:00
Eddie Hung
4311b9b583 Blackboxes 2019-05-26 11:32:02 -07:00
Eddie Hung
ae89e6ab26 Add whitebox support to DRAM 2019-05-23 08:58:57 -07:00
Eddie Hung
ee8435b820 Instead of MUXCY/XORCY use CARRY4 (with timing) 2019-05-21 16:19:45 -07:00
Eddie Hung
79fb291dbe Cleanup, call pmux2shiftx even without -nosrl 2019-04-22 12:14:37 -07:00
Eddie Hung
13ad19482f Merge remote-tracking branch 'origin' into xc7srl 2019-04-20 10:41:43 -07:00
Keith Rothman
1f9235ede5 Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-12 09:35:15 -07:00
Keith Rothman
e107ccdde8 Fix LUT6_2 definition. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-09 11:43:19 -07:00
Keith Rothman
5e0339855f Add additional cells sim models for core 7-series primatives. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-09 09:01:53 -07:00
Eddie Hung
f1a8e8a480 Merge remote-tracking branch 'origin/master' into xc7srl 2019-03-14 08:59:19 -07:00
Keith Rothman
3e16f75bc6 Revert FF models to include IS_x_INVERTED parameters. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 14:41:21 -08:00
Keith Rothman
3090951d54 Changes required for VPR place and route synth_xilinx. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 12:02:27 -08:00
Eddie Hung
73ddab6960 Add SRL16 and SRL32 sim models 2019-02-28 13:56:22 -08:00
Clifford Wolf
6991c132b5 Add Xilinx RAM64X1D and RAM128X1D simulation models 2018-03-07 17:31:48 +01:00
Clifford Wolf
853e949c0e Disabled (unused) Xilinx tristate buffers 2015-02-04 16:33:59 +01:00
Clifford Wolf
816fe6bbe0 Added Xilinx example for Basys3 board 2015-02-01 17:09:34 +01:00
Clifford Wolf
909a95182b Fixed xilinx FDSE sim model 2015-01-24 11:03:22 +01:00
Clifford Wolf
7031231145 Added MUXCY and XORCY support to synth_xilinx 2015-01-17 15:39:54 +01:00
Clifford Wolf
fd8c8d4fd3 Added FF cells to xilinx/cells_sim.v 2015-01-16 14:59:40 +01:00
Clifford Wolf
38dfc5c580 added minimalistic xilinx sim models 2015-01-08 00:05:11 +01:00