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Author SHA1 Message Date
N. Engelhardt
7c4e580f8f
Merge pull request #2054 from boqwxp/fix-smtbmc 
smtbmc: Fix return status handling.
 2020-05-20 08:55:36 +02:00
Alberto Gonzalez
1053032a81
smtbmc: Fix typo in error message. 
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
 2020-05-19 16:13:44 +00:00
Marcelina Kościelnicka
aee439360b Add force_downto and force_upto wire attributes. 
Fixes #2058.
 2020-05-19 01:42:40 +02:00
Eddie Hung
2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff 
abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
 2020-05-18 08:06:50 -07:00
Alberto Gonzalez
049e4caceb
firrtl: Accept techmapped cell types in FIRRTL backend. 2020-05-17 10:03:11 +00:00
Claire Wolf
fa8cb3e35d Revert "Add support for non-power-of-two mem chunks in verific importer" 
This reverts commit 173aa27ca5.
 2020-05-17 11:31:11 +02:00
Alberto Gonzalez
8297afe925
log: Use dict instead of std::vector<std::pair> for log_expect_{error, warning, log} to better express the intent that each element is unique. 2020-05-15 00:55:32 +00:00
Eddie Hung
67fc0c3698 abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_ 
instead of moving them to $__ prefix
 2020-05-14 16:44:35 -07:00
Eddie Hung
7101ef550b verilog: attributes before task enable (but 13 s/r conflicts) 2020-05-14 16:10:11 -07:00
Eddie Hung
e7fd8912f0 tests: attributes before task enable 2020-05-14 16:09:41 -07:00
Eddie Hung
07eecff9cc
Merge pull request #2055 from YosysHQ/eddie/logger_multiple 
logger: fix for multiple calls with same pattern
 2020-05-14 15:30:08 -07:00
Eddie Hung
7b3a4a1fff opt_expr: Sx to Sz; spotted by @Xiretza 2020-05-14 12:14:23 -07:00
Eddie Hung
73b7ea713c
Merge pull request #1994 from YosysHQ/eddie/fix_bug1758 
opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
 2020-05-14 11:56:22 -07:00
Eddie Hung
425867d175 logger: clean up doc 2020-05-14 10:38:31 -07:00
Eddie Hung
02df0198b6 abc9_ops: -prep_hier to create unmap module that removes Q's (* init *) 2020-05-14 10:33:57 -07:00
Eddie Hung
13f9d65b6f abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it 2020-05-14 10:33:57 -07:00
Eddie Hung
fa31e84112 Fix broken test when ignoring abc9_flop with init == 1'b1 2020-05-14 10:33:57 -07:00
Eddie Hung
97a0a04314 abc9_ops/xaiger: further reducing Module::derive() calls by ... 
replacing _all_ (* abc9_box *) instantiations with their derived types
 2020-05-14 10:33:57 -07:00
Eddie Hung
e79127fceb Cleanup; reduce Module::derive() calls 2020-05-14 10:33:57 -07:00
Eddie Hung
cea614f5ae ecp5: latches_map.v if *not* -asyncprld 2020-05-14 10:33:57 -07:00
Eddie Hung
fdc340db8e ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.v 2020-05-14 10:33:57 -07:00
Eddie Hung
39759d5f0e ecp5: fix rebase mistake 2020-05-14 10:33:57 -07:00
Eddie Hung
8d34aee3d5 abc9: update to =_$abc9_flops pattern which includes whiteboxes 2020-05-14 10:33:57 -07:00
Eddie Hung
f652a9c11c abc9_ops: update docs 2020-05-14 10:33:57 -07:00
Eddie Hung
ca4f8c9444 xilinx: gate specify/attributes from iverilog 2020-05-14 10:33:57 -07:00
Eddie Hung
57c478c537 abc9: only do +/abc9_map if `DFF 2020-05-14 10:33:57 -07:00
Eddie Hung
2946bb60e9 abc9: rework submod -- since it won't move (* keep *) cells 2020-05-14 10:33:56 -07:00
Eddie Hung
8cda29137e ecp5: TRELLIS_FF bypass path only in async mode 2020-05-14 10:33:56 -07:00
Eddie Hung
7146c0339e timinginfo: ignore $specify2 cells if EN is false 2020-05-14 10:33:56 -07:00
Eddie Hung
6c34945371 xilinx/ice40/ecp5: zinit requires selected wires, so select them all 2020-05-14 10:33:56 -07:00
Eddie Hung
b65610fb62 abc9_ops: move assert 2020-05-14 10:33:56 -07:00
Eddie Hung
ed7cb0b095 abc9: put 'aigmap' back 2020-05-14 10:33:56 -07:00
Eddie Hung
a323881e15 xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells 2020-05-14 10:33:56 -07:00
Eddie Hung
b3e2538a14 abc9_ops: fix bypass boxes using (* abc9_bypass *) 2020-05-14 10:33:56 -07:00
Eddie Hung
d5a8aaba8c abc9_ops: tidy up, suppress error if no boxes/holes 2020-05-14 10:33:56 -07:00
Eddie Hung
e2044fd9c7 abc9_ops: -prep_delays to not insert delay box if input connection is const 2020-05-14 10:33:56 -07:00
Eddie Hung
8b5fb99245 abc9_ops: cleanup; -prep_dff -> -prep_dff_submod 2020-05-14 10:33:56 -07:00
Eddie Hung
7cd3f4a79b abc9_ops: add -prep_bypass for auto bypass boxes; refactor 
Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
 2020-05-14 10:33:56 -07:00
Eddie Hung
bb840cca9c abc9_ops: -reintegrate to handle $_FF_; cleanup 2020-05-14 10:33:56 -07:00
Eddie Hung
e357b40e7a xaiger: no longer use nonstandard even/odd to designate +ve/-ve polarity 2020-05-14 10:33:56 -07:00
Eddie Hung
4017cc6380 aiger: -xaiger to return $_FF_ flops 2020-05-14 10:33:56 -07:00
Eddie Hung
722540dbf9 abc9: not enough to techmap_fail on (* init=1 *), hide them using $__ 2020-05-14 10:33:56 -07:00
Eddie Hung
5ad3a85288 abc9: test to use box file instead of auto 2020-05-14 10:33:56 -07:00
Eddie Hung
c50601e35e abc9: restore selected_modules() 2020-05-14 10:33:56 -07:00
Eddie Hung
8fbb55f4ab synth_*: no need to explicitly read +/abc9_model.v 2020-05-14 10:33:56 -07:00
Eddie Hung
63246a5c0e Revert "Merge pull request #1917 from YosysHQ/eddie/abc9_delay_check" 
This reverts commit 759283fa65, reversing
changes made to f41c7ccfff.
 2020-05-14 10:33:56 -07:00
Eddie Hung
48052ad813 abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too 2020-05-14 10:33:56 -07:00
Eddie Hung
7812a2959b kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero 2020-05-14 10:33:56 -07:00
Eddie Hung
4cec21b93e abc9_ops: -prep_dff_map to error if async flop found 2020-05-14 10:33:56 -07:00
Eddie Hung
6c66030dfb Uncomment negative setup times; clamp to zero for connectivity 2020-05-14 10:33:56 -07:00