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9 commits

Author SHA1 Message Date
Eddie Hung
15188033da Add variable length support to xilinx_srl 2019-08-21 17:34:40 -07:00
Eddie Hung
6d76ae4c65 Rename pattern to fixed 2019-08-21 15:46:58 -07:00
Eddie Hung
b0a3b430bf attribute -> attr 2019-08-21 15:44:07 -07:00
Eddie Hung
61b4d7ae13 Use Cell::has_keep_attribute() 2019-08-21 15:41:46 -07:00
Eddie Hung
6fa9e03e4c xilinx_srl to support FDRE and FDRE_1 2019-08-21 15:35:29 -07:00
Eddie Hung
1c7d721558 Reject if not minlen from inside pattern matcher 2019-08-21 14:26:24 -07:00
Eddie Hung
cab2bd083e Get wire via SigBit 2019-08-21 13:47:47 -07:00
Eddie Hung
52fea5b658 Respect \keep on cells or wires 2019-08-21 13:42:03 -07:00
Eddie Hung
0250712486 Initial progress on xilinx_srl 2019-08-21 12:50:49 -07:00