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2784 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Clifford Wolf
4c733301e6 Fixed cstr_buf for std::string with small string optimization 2015-06-11 13:39:49 +02:00
Clifford Wolf
3a6abc9bf6 Improvements in cellaigs.cc and "json -aig" 2015-06-11 10:48:16 +02:00
Clifford Wolf
1ae360cf72 AigMaker refactoring 2015-06-10 23:00:12 +02:00
Clifford Wolf
e534881794 Added "json -aig" 2015-06-10 08:13:56 +02:00
Clifford Wolf
56d4822719 Renamed "aig" to "aigmap" 2015-06-10 07:24:26 +02:00
Clifford Wolf
85287295b2 Fixed cellaigs port extending 2015-06-10 07:16:30 +02:00
Clifford Wolf
66f9ee412a Added "aig" pass 2015-06-09 22:33:26 +02:00
Clifford Wolf
9500b564ac synth_ice40 now flattens by default 2015-06-09 20:28:17 +02:00
Clifford Wolf
e49e2662aa Added cellaigs API 2015-06-09 09:54:22 +02:00
Clifford Wolf
b57cb4a7fe Merge clock inverters in memory_dff 2015-06-09 07:25:12 +02:00
Clifford Wolf
c88be7bae5 Merge branch 'verilog-backend-memV2' of github.com:wluker/yosys 2015-06-09 06:42:07 +02:00
luke whittlesey
2f90499e3d $mem cell in verilog backend : grouped writes by clock 2015-06-08 17:35:40 -04:00
Clifford Wolf
de4f4dad3c Fixed "avail_parameters" handling in module clone/copy 2015-06-08 14:49:34 +02:00
Clifford Wolf
98650a0609 Added log_dump() support for IdStrings 2015-06-08 14:49:02 +02:00
Clifford Wolf
13983e8318 Fixed handling of parameters with reversed range 2015-06-08 14:03:06 +02:00
luke whittlesey
a8fe040906 Bug fix in $mem verilog backend + changed tests/bram flow of make test. 2015-06-04 16:12:40 -04:00
Clifford Wolf
08f9b38a9c Added opt_share -share_all 2015-05-31 14:24:34 +02:00
Clifford Wolf
09ef279b60 Added iCE40 PLL cells 2015-05-31 13:10:43 +02:00
Clifford Wolf
522705cc28 Added liberty dont_use support to dfflibmap 2015-05-31 07:51:12 +02:00
Clifford Wolf
99b8746d27 Fixed signedness of genvar expressions 2015-05-29 20:08:00 +02:00
Clifford Wolf
c329233f0d Added output args to synth_ice40 2015-05-26 17:08:53 +02:00
Clifford Wolf
08a4af3cde Improvements in BLIF front-end 2015-05-24 08:03:21 +02:00
Clifford Wolf
313f570fcc improved ice40 SB_IO sim model 2015-05-23 10:17:03 +02:00
Clifford Wolf
9f772eb970 Improved "flatten" handlings of inout ports 2015-05-23 10:14:53 +02:00
Clifford Wolf
4b6221478e Added simple $dlatch support to opt_rmdff 2015-05-23 09:45:48 +02:00
Clifford Wolf
264eb8eb6e Added ice40 SB_IO sim model 2015-05-23 09:30:24 +02:00
Clifford Wolf
98bceed0da Merge branch 'master' of github.com:cliffordwolf/yosys 2015-05-22 08:23:03 +02:00
Clifford Wolf
e122c2644e preserve used $-wires with init attribute in opt_clean 2015-05-22 08:20:29 +02:00
Clifford Wolf
4744bb95fb Some fixes for $mem in verilog back-end 2015-05-20 13:55:50 +02:00
Clifford Wolf
6061b7bd58 bugfix in blif front-end 2015-05-18 11:15:49 +02:00
Clifford Wolf
83499dc1ba added vloghtb test_febe.sh 2015-05-17 19:54:00 +02:00
Clifford Wolf
3ecb2bf067 Improved .latch support in BLIF front-end 2015-05-17 18:58:24 +02:00
Clifford Wolf
2cc4e75914 Added read_blif command 2015-05-17 15:25:03 +02:00
Clifford Wolf
e5116eeb77 Generalized blifparse API 2015-05-17 15:10:37 +02:00
Clifford Wolf
7dad017c9c abc/blifparse files reorganization 2015-05-17 14:44:28 +02:00
Clifford Wolf
61512b6f41 Verific build fixes 2015-05-17 08:19:52 +02:00
Clifford Wolf
c2f30e0de4 Added .barbuf support to abc BLIF parser 2015-05-13 06:45:12 +02:00
Clifford Wolf
dae00e1d83 changed file() to open() in python scripts 2015-05-11 21:58:21 +02:00
Clifford Wolf
42348cddd9 Merge pull request #63 from wluker/verilog-backend-mem 
Fixed bug in $mem cell verilog code generation.
 2015-05-11 21:38:06 +02:00
luke whittlesey
3bb5f064b8 Fixed bug in $mem cell verilog code generation. 2015-05-11 14:05:18 -04:00
Clifford Wolf
9e56739634 Disabled broken $mem support in verilog backend 2015-05-10 21:38:41 +02:00
Clifford Wolf
e47218e9ea Merge pull request #62 from wluker/verilog-backend-mem 
Added support for $mem cells in the verilog backend.
 2015-05-10 21:23:59 +02:00
luke whittlesey
6de8fea2c7 Made changes recommended by Clifford Wolf ... 
Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used
dict<> instead of std::map, and used RTLIL::SigSpec instead of
std::vector.
 2015-05-10 11:33:24 -04:00
luke whittlesey
2c1e150297 Verilog backend for $mem cells should now be able to handle different 
write-enable bits and RD_TRANSPARENT parameter settings.
 2015-05-08 15:29:51 -04:00
luke whittlesey
c0b68f4848 Added support for $mem cells in the verilog backend. 2015-05-07 13:03:09 -04:00
Clifford Wolf
7462618591 Fixed memory_unpack for initialized memories 2015-04-29 19:55:32 +02:00
Clifford Wolf
96be31de89 Preserve important attributes in splitnets 2015-04-29 07:44:57 +02:00
Clifford Wolf
f483dce7c2 Added $eq/$neq -> $logic_not/$reduce_bool optimization 2015-04-29 07:28:15 +02:00
Clifford Wolf
9d067fecea ice40_opt bugfix 2015-04-27 11:36:13 +02:00
Clifford Wolf
310fde197e iCE40: SB_CARRY const fold -> unmap SB_LUT 2015-04-27 10:27:50 +02:00