12 commits

Author	SHA1	Message	Date
Eddie Hung	e18aeda7ed	Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards ... Just like Verilog...	2020-01-27 14:02:13 -08:00
Eddie Hung	b178761551	ice40: reduce ABC9 internal fanout warnings with a param for CI->I3	2020-01-24 11:59:48 -08:00
Eddie Hung	36a88be609	ice40_wrapcarry -unwrap to preserve 'src' attribute	2019-12-09 14:28:54 -08:00
Eddie Hung	bbdf2452b3	-unwrap to create $lut not SB_LUT4 for opt_lut	2019-12-09 13:27:09 -08:00
Eddie Hung	500ed9b501	Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4	2019-12-09 12:45:22 -08:00
Eddie Hung	e05372778a	ice40_wrapcarry to really preserve attributes via -unwrap option	2019-12-09 11:48:28 -08:00
Eddie Hung	946d5854c0	Drop keep=0 attributes on SB_CARRY	2019-12-06 17:27:47 -08:00
Eddie Hung	a7e0cca480	Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER	2019-12-05 07:01:18 -08:00
Eddie Hung	5897b918b3	ice40_wrapcarry to preserve SB_CARRY's attributes	2019-12-03 14:48:11 -08:00
Eddie Hung	12c692f6ed	Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" ... This reverts commit c851dc1310, reversing changes made to f54bf1631f.	2019-08-12 12:06:45 -07:00
David Shah	f9020ce2b3	Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"	2019-08-10 17:14:48 +01:00
Eddie Hung	675c1d4218	Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER	2019-08-07 16:29:38 -07:00