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4 commits

Author SHA1 Message Date
gatecat 5dba138c87 intel_alm: Add IO buffer insertion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 22:37:06 +01:00
Dan Ravensloft 034b9ec716 intel: move Cyclone V support to intel_alm 2020-08-20 18:25:05 +02:00
Dan Ravensloft 4ca5f9799b intel_alm: cleanup duplication 2020-04-24 11:26:48 +02:00
Dan Ravensloft 2e37e62e6b synth_intel_alm: alternative synthesis for Intel FPGAs 
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
 2020-04-15 11:40:41 +02:00