mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-05-06 07:15:48 +00:00
Code Activity
10079 commits 107 branches 54 tags 52 MiB
Commit graph

5 commits

Author SHA1 Message Date
Dan Ravensloft
4d9d90079c intel_alm: add additional ABC9 timings 2020-07-23 11:57:07 +01:00
Lofty
a3a90f6377 Revert "intel_alm: direct M10K instantiation" 
This reverts commit 09ecb9b2cf.
 2020-07-13 18:05:38 +02:00
Dan Ravensloft
09ecb9b2cf intel_alm: direct M10K instantiation 2020-07-05 23:28:59 +02:00
Dan Ravensloft
83cde2d02b intel_alm: ABC9 sequential optimisations 2020-07-04 19:45:10 +02:00
Dan Ravensloft
5b779f7f4e intel_alm: direct LUTRAM cell instantiation 
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.

While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
 2020-05-07 21:03:13 +02:00