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Author	SHA1	Message	Date
Clifford Wolf	9329a76818	Various bug fixes (related to $macc model testing)	2014-09-06 20:30:46 +02:00
Clifford Wolf	98e6463ca7	Added $macc eval model	2014-09-06 19:44:28 +02:00
Clifford Wolf	fa64942018	Added $macc SAT model	2014-09-06 19:44:11 +02:00
Clifford Wolf	680eaaac41	Fixed $clog2 (off by one error)	2014-09-06 19:31:04 +02:00
Clifford Wolf	bff4706b62	Added $macc simlib model (also use as techmap rule for now)	2014-09-06 17:59:12 +02:00
Clifford Wolf	deff416ea7	Fixed assignment of out-of bounds array element	2014-09-06 17:58:27 +02:00
Clifford Wolf	b847ec8a0b	Added $macc cell type	2014-09-06 15:47:46 +02:00
Clifford Wolf	76f8128123	Fixed autotest for non-basename arguments	2014-09-06 12:10:57 +02:00
Clifford Wolf	34af6a1303	Merge branch 'master' of github.com:cliffordwolf/yosys	2014-09-06 11:46:44 +02:00
Clifford Wolf	e1743b3bac	Added "test_cell -script"	2014-09-06 11:46:07 +02:00
Clifford Wolf	652345c9cd	Merge pull request #38 from rubund/master ... Corrected spelling mistakes found by lintian	2014-09-06 10:15:47 +02:00
Ruben Undheim	79cbf9067c	Corrected spelling mistakes found by lintian	2014-09-06 08:47:06 +02:00
Clifford Wolf	01ef34c147	Added tests/various/constmsk_test.ys	2014-09-04 15:07:30 +02:00
Clifford Wolf	f5a40e7043	Fixed "opt_const -fine" for $pos cells	2014-09-04 08:55:58 +02:00
Clifford Wolf	8927aa6148	Removed $bu0 cell type	2014-09-04 02:07:52 +02:00
Clifford Wolf	b9cb483f3e	Using $pos models for $bu0	2014-09-03 21:20:59 +02:00
Clifford Wolf	5733f4a39d	Fixed "test_cells -vlog"	2014-09-03 13:43:37 +02:00
Clifford Wolf	50ac284823	Fixes in $alu SAT- and eval-models	2014-09-03 13:39:46 +02:00
Clifford Wolf	635b922afe	Undef-related fixes in simlib $alu model	2014-09-02 23:21:59 +02:00
Clifford Wolf	f1869667ca	Improvements in "test_cell -vlog"	2014-09-02 23:21:15 +02:00
Clifford Wolf	66bf2bb92e	Added test_cell -vlog	2014-09-02 22:49:43 +02:00
Clifford Wolf	da360771a1	Create a default selection stack in RTLIL::Design::Design()	2014-09-02 22:49:24 +02:00
Clifford Wolf	c38283dbd0	Small bug fixes in $not, $neg, and $shiftx models	2014-09-02 17:48:41 +02:00
Clifford Wolf	acd7a99aef	Added SAT testing to test_cell eval stage	2014-09-02 17:28:13 +02:00
Ahmed Irfan	2446b6fbef	added $pmux cell translation	2014-09-02 14:47:51 +02:00
Clifford Wolf	37fe7c7bdf	Removed references to yosys-svgviewer from docs	2014-09-02 04:03:06 +02:00
Clifford Wolf	ee29ae2206	Removed yosys-svgviewer	2014-09-02 03:52:46 +02:00
Clifford Wolf	9f00a0cd2d	Using "xdot" instead of "yosys-svgviewer" in show command	2014-09-02 03:28:46 +02:00
Clifford Wolf	630befdf6d	Added $alu support to test_cell	2014-09-01 16:36:04 +02:00
Clifford Wolf	2fcf66b91d	Added ConstEval model for $alu cells	2014-09-01 16:35:46 +02:00
Clifford Wolf	bae09dca2b	Added SAT model for $alu cells	2014-09-01 16:35:25 +02:00
Clifford Wolf	9923762461	Fixed "test_cell -simlib all"	2014-09-01 15:37:56 +02:00
Clifford Wolf	c7f81e4e49	Added "test_cell -simlib -v"	2014-09-01 15:37:21 +02:00
Clifford Wolf	826fdb34d8	Added "techmap -autoproc"	2014-09-01 15:36:29 +02:00
Clifford Wolf	27a1bfbec6	Fixes in old SAT example.ys	2014-09-01 11:45:47 +02:00
Clifford Wolf	d5148f2e01	Moved "share" and "wreduce" to passes/opt/	2014-09-01 11:45:26 +02:00
Clifford Wolf	e07698818d	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data	2014-09-01 11:36:02 +02:00
Clifford Wolf	e3664066d5	Added eval testing to test_cell	2014-08-31 18:08:42 +02:00
Clifford Wolf	83ec3fa204	Fixed return size of const_*() eval functions	2014-08-31 18:08:26 +02:00
Clifford Wolf	be44157c0f	Added RTLIL::Const::size()	2014-08-31 18:07:48 +02:00
Clifford Wolf	a1c7d4a8e2	Added eval model for $lut cells	2014-08-31 17:43:31 +02:00
Clifford Wolf	0b6769af3f	Typo fixes in cell->*Param() API	2014-08-31 17:43:31 +02:00
Clifford Wolf	8649b57b6f	Added $lut support in test_cell, techmap, satgen	2014-08-31 17:43:31 +02:00
Clifford Wolf	2a1b08aeb3	Added design->scratchpad	2014-08-30 19:37:12 +02:00
Clifford Wolf	4724d94fbc	Added $alu cell type	2014-08-30 18:59:05 +02:00
Clifford Wolf	88db09255b	Added autotest -e (do not use -noexpr on write_verilog)	2014-08-30 18:34:07 +02:00
Clifford Wolf	6ff46323a3	Improved write address decoder generation memory_map	2014-08-30 18:18:15 +02:00
Clifford Wolf	dfbd7dd15a	Fixed module->addPmux()	2014-08-30 18:17:22 +02:00
Clifford Wolf	66763fad4e	Using worker class in memory_map	2014-08-30 17:39:08 +02:00
Clifford Wolf	eb571cba6a	Replaced $__alu CO/CS outputs with full-width CO output	2014-08-30 15:12:39 +02:00