mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 20:38:44 +00:00
Code Activity
11525 commits 97 branches 53 tags 41 MiB
Commit graph

3 commits

Author SHA1 Message Date
Maciej Dudek cfddef5d7d Fixes xc7 BRAM36s 
UG473 from Xilinx states that 15 bit should always be set if RAMB isn't in cascade mode.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-07-30 16:17:22 +02:00
Marcin Kościelnicki 30854b9c7f xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. 2020-02-07 01:00:29 +01:00
Marcin Kościelnicki ce250b341c synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
Renamed from techlibs/xilinx/brams_map.v (Browse further)