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Code Activity
15744 commits 124 branches 58 tags 49 MiB
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8 commits

Author SHA1 Message Date
Robert O'Callahan
e0ae7b7af4 Remove .c_str() calls from log()/log_error() 
There are some leftovers, but this is an easy regex-based approach that removes most of them.
 2025-09-11 20:59:37 +00:00
whitequark
7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Eddie Hung
956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
R. Ou
7932672fc2 coolrunner2: Attempt to give wires/cells more meaningful names 2020-03-02 01:40:57 -08:00
R. Ou
b9c98e0100 coolrunner2: Fix invalid multiple fanouts of XOR/OR gates 
In some cases where multiple output pins share identical combinatorial
logic, yosys would only generate one $sop cell and therefore one
MACROCELL_XOR cell to try to feed the multiple sinks. This is not valid,
so make the fixup pass duplicate cells when necessary. For example,
fixes the following code:

module top(input a, input b, input clk_, output reg o, output o2);

wire clk;

BUFG bufg0 (
    .I(clk_),
    .O(clk),
);

always @(posedge clk)
    o = a ^ b;
assign o2 = a ^ b;

endmodule
 2020-03-02 01:07:15 -08:00
R. Ou
a618004897 coolrunner2: Fix packed register+input buffer insertion 
The register will be packed with the input buffer if and only if the
input buffer doesn't have any other loads.
 2020-03-02 00:32:57 -08:00
R. Ou
a6aeee4e1a coolrunner2: Insert many more required feedthrough cells 2020-03-01 16:56:21 -08:00
R. Ou
6a0682f5a0 coolrunner2: Separate and improve buffer cell insertion pass 
The new pass will contain all of the logic for inserting "passthrough"
product term and XOR cells as appropriate for the architecture. For
example, this commit fixes connecting an input pin directly to another
output pin with no logic in between.
 2020-02-16 20:25:46 -08:00