868 commits

Author	SHA1	Message	Date
Eddie Hung	28bf712372	Wrap arrival functions inside `YOSYS too	2020-01-06 11:55:56 -08:00
Eddie Hung	27c150bfcc	Fix return value of arrival time functions, fix word	2020-01-06 11:39:08 -08:00
Eddie Hung	020606f81c	Merge remote-tracking branch 'origin/eddie/abc9_refactor' into xaig_arrival_required	2020-01-06 09:44:00 -08:00
Eddie Hung	bac1e65a9c	Fix spacing	2020-01-02 17:21:54 -08:00
Eddie Hung	50b68777d3	Drive $[ABCD] explicitly	2020-01-02 13:28:37 -08:00
Eddie Hung	a051801b72	synth_xilinx -dff to work with abc too	2020-01-02 12:53:26 -08:00
Eddie Hung	3012e9eebc	Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor	2020-01-02 12:48:07 -08:00
Eddie Hung	b454735bea	Merge remote-tracking branch 'origin/master' into xaig_dff	2020-01-02 12:44:06 -08:00
Eddie Hung	ec1756c094	Update comments	2020-01-02 12:39:52 -08:00
Eddie Hung	8e507bd807	abc9 -keepff -> -dff; refactor dff operations	2020-01-02 12:36:54 -08:00
Eddie Hung	d6242be802	Merge pull request #1601 from YosysHQ/eddie/synth_retime ... "abc -dff" to no longer retime by default	2020-01-02 08:46:24 -08:00
Eddie Hung	d0d3ab8f67	ifndef __ICARUS__ -> ifdef YOSYS	2020-01-01 17:33:47 -08:00
Eddie Hung	3d98a96273	ifdef __ICARUS__ -> ifndef YOSYS	2020-01-01 17:33:10 -08:00
Eddie Hung	db04161eca	Rework abc9's DSP48E1 model	2020-01-01 17:30:26 -08:00
Eddie Hung	0e95756e96	Clamp -46ps for FDPE* too	2020-01-01 08:39:00 -08:00
Eddie Hung	c40b1aae42	Restore abc9 -keepff	2020-01-01 08:34:43 -08:00
Eddie Hung	44d9fb0e7c	Re-arrange FD order	2019-12-31 18:47:38 -08:00
Eddie Hung	35c659be74	Cleanup xilinx boxes	2019-12-31 18:29:44 -08:00
Eddie Hung	6b825c719b	Update abc9_xc7.box comments	2019-12-31 15:25:46 -08:00
Eddie Hung	4cdba00e25	FDCE ports to be alphabetical	2019-12-31 15:24:02 -08:00
Eddie Hung	b4663a987b	Fix attributes on $__ABC9_ASYNC[01] whitebox	2019-12-31 11:14:11 -08:00
Eddie Hung	789211d9b3	Fix incorrect $__ABC9_ASYNC[01] box	2019-12-31 11:13:50 -08:00
Eddie Hung	543bd2de6c	Update timings for Xilinx S7 cells	2019-12-30 14:36:07 -08:00
Eddie Hung	eb4e767053	Do not offset FD* box timings due to -46ps Tsu	2019-12-30 14:35:10 -08:00
Eddie Hung	405e974fe5	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-12-30 14:31:42 -08:00
Eddie Hung	a038294a87	Tidy up abc9_map.v	2019-12-30 14:19:29 -08:00
Eddie Hung	d7ada66497	Add "synth_xilinx -dff" option, cleanup abc9	2019-12-30 14:13:16 -08:00
Eddie Hung	79448f9be0	Update doc that "-retime" calls abc with "-dff -D 1"	2019-12-30 13:28:29 -08:00
Eddie Hung	aa6d06c1b5	Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well"" ... This reverts commit 6008bb7002.	2019-12-30 13:28:29 -08:00
Miodrag Milanovic	8c3de1d4bd	Merge remote-tracking branch 'origin/master' into iopad_default	2019-12-28 16:23:31 +01:00
Eddie Hung	b7afafde22	Consistency	2019-12-27 14:52:26 -08:00
Eddie Hung	4eaa45091c	Update some abc9_arrival times, add abc9_required times	2019-12-27 14:47:50 -08:00
Marcin Kościelnicki	13a3041030	Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen ... xilinx_dsp: Initial DSP48A/DSP48A1 support.	2019-12-25 16:18:44 +01:00
Marcin Kościelnicki	dadaf7ed78	xilinx: Test our DSP48A/DSP48A1 simulation models.	2019-12-23 20:36:43 +01:00
Marcin Kościelnicki	666c6128a9	xilinx_dsp: Initial DSP48A/DSP48A1 support.	2019-12-22 20:51:14 +01:00
Miodrag Milanovic	436fea9e69	Addressed review comments	2019-12-21 20:23:23 +01:00
Miodrag Milanovic	1937091f62	iopad no op for compatibility with old scripts	2019-12-21 13:21:45 +01:00
Miodrag Milanovic	2fcf683af4	Make iopad option default for all xilinx flows	2019-12-21 11:56:41 +01:00
Eddie Hung	d3fc94405f	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-12-20 14:07:23 -08:00
Eddie Hung	5986a4df40	Add abc9_arrival times for RAM{32,64}M	2019-12-20 14:06:59 -08:00
Eddie Hung	1ea1e8e54f	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-12-20 13:56:13 -08:00
Eddie Hung	7928eb113c	Add RAM{32,64}M to abc9_map.v	2019-12-20 13:41:23 -08:00
Eddie Hung	10e82e103f	Revert "Optimise write_xaiger"	2019-12-20 12:05:45 -08:00
Eddie Hung	45f0f1486b	Add RAM{32,64}M to abc9_map.v	2019-12-19 11:24:39 -08:00
Eddie Hung	979bf36fb0	Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t	2019-12-19 11:23:41 -08:00
Eddie Hung	94f15f023c	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-12-19 10:29:40 -08:00
Eddie Hung	df626ee7ab	Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup ... Optimise write_xaiger	2019-12-19 12:24:03 -05:00
Marcin Kościelnicki	8b2c9f4518	xilinx: Add simulation models for remaining CLB primitives.	2019-12-19 18:04:04 +01:00
Marcin Kościelnicki	561ae1c5c4	xilinx_dffopt: Keep order of LUT inputs. ... See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549	2019-12-19 18:01:43 +01:00
Marcin Kościelnicki	a235250403	xilinx: Add xilinx_dffopt pass (#1557)	2019-12-18 13:43:43 +01:00