117 commits

Author	SHA1	Message	Date
Clifford Wolf	c8763301b4	Added $div and $mod technology mapping	2013-08-09 17:09:24 +02:00
Clifford Wolf	3650fd7fbe	More fixes in ternary op sign handling	2013-07-12 13:13:04 +02:00
Clifford Wolf	ded769c98c	Fixed sign handling in ternary operator	2013-07-12 01:15:37 +02:00
Clifford Wolf	b380c8c790	Another vloghammer related bugfix	2013-07-11 19:24:59 +02:00
Clifford Wolf	5dab327b30	More fixes in ast expression sign/width handling	2013-07-09 23:41:43 +02:00
Clifford Wolf	618b2ac994	Merge branch 'master' of github.com:cliffordwolf/yosys	2013-07-09 19:00:10 +02:00
Clifford Wolf	7daeee340a	Fixed shift ops with large right hand side	2013-07-09 18:59:59 +02:00
Clifford Wolf	00a6c1d9a5	Major redesign of expr width/sign detecion (verilog/ast frontend)	2013-07-09 14:31:57 +02:00
Clifford Wolf	e8da3ea7b6	Fixed another bug found using vloghammer	2013-07-07 16:49:30 +02:00
Clifford Wolf	56432a920f	Added defparam support to Verilog/AST frontend	2013-07-04 14:12:33 +02:00
Clifford Wolf	e0c408cb4a	Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values	2013-04-13 21:19:10 +02:00
Clifford Wolf	5640b7d607	Added test cases from 2012 paper on comparison of foss verilog synthesis tools	2013-03-31 11:17:56 +02:00
Clifford Wolf	d9bc024d29	Renamed hansimem.v test case to mem_arst.v	2013-03-24 15:25:08 +01:00
Clifford Wolf	c3c9e5a02f	Added hansimem testcase (memory with async reset)	2013-03-24 10:40:40 +01:00
Johann Glaser	3cfbc18601	added ckeck for Icarus Verilog, otherwise the tests are silently stopped ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2013-03-17 09:05:15 +01:00
Clifford Wolf	2d9cbd3b02	added more .gitignore files (make test)	2013-01-05 11:35:52 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00