110 commits

Author	SHA1	Message	Date
Fabio Utzig	fff6f00b3c	Enable bison to be customized	2015-01-08 09:56:20 -02:00
Clifford Wolf	1bd67d792e	Define YOSYS and SYNTHESIS in preproc	2015-01-02 17:11:54 +01:00
Clifford Wolf	7751c491fb	Improved some warning messages	2014-12-27 03:40:27 +01:00
Clifford Wolf	1282a113da	Fixed supply0/supply1 with many wires	2014-12-11 13:56:20 +01:00
Clifford Wolf	76c83283c4	Fixed minor bug in parsing delays	2014-11-24 14:48:07 +01:00
Clifford Wolf	56c7d1e266	Fixed two minor bugs in constant parsing	2014-11-24 14:39:24 +01:00
Clifford Wolf	87333f3ae2	Added warning for use of 'z' constants in HDL	2014-11-14 19:59:50 +01:00
Clifford Wolf	4e5350b409	Fixed parsing of nested verilog concatenation and replicate	2014-11-12 19:10:35 +01:00
Clifford Wolf	fe829bdbdc	Added log_warning() API	2014-11-09 10:44:23 +01:00
Clifford Wolf	a21481b338	Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."	2014-10-30 14:01:02 +01:00
Clifford Wolf	f9c096eeda	Added support for task and function args in parentheses	2014-10-27 13:21:57 +01:00
Clifford Wolf	c5eb5e56b8	Re-introduced Yosys::readsome() helper function ... (f.read() + f.gcount() made problems with lines > 16kB)	2014-10-23 10:58:36 +02:00
Clifford Wolf	3838856a9e	Print "SystemVerilog" in "read_verilog -sv" log messages	2014-10-16 10:31:54 +02:00
Clifford Wolf	f65e1c309f	Updated .gitignore file for ilang and verilog frontends	2014-10-15 01:14:38 +02:00
Clifford Wolf	c3e9922b5d	Replaced readsome() with read() and gcount()	2014-10-15 01:12:53 +02:00
William Speirs	fad0b0c506	Updated lexers & parsers to include prefixes	2014-10-15 00:48:19 +02:00
Clifford Wolf	8263f6a74a	Fixed win32 troubles with f.readsome()	2014-10-11 11:36:22 +02:00
Clifford Wolf	bbd808072b	Added format __attribute__ to stringf()	2014-10-10 17:22:08 +02:00
Clifford Wolf	4569a747f8	Renamed SIZE() to GetSize() because of name collision on Win32	2014-10-10 17:07:24 +02:00
Clifford Wolf	f9a307a50b	namespace Yosys	2014-09-27 16:17:53 +02:00
Clifford Wolf	58367cd87a	Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore	2014-08-23 15:14:58 +02:00
Clifford Wolf	19cff41eb4	Changed frontend-api from FILE to std::istream	2014-08-23 15:03:55 +02:00
Clifford Wolf	e218f0eacf	Added support for non-standard <plugin>:<c_name> DPI syntax	2014-08-22 14:30:29 +02:00
Clifford Wolf	6c5cafcd8b	Added support for DPI function with different names in C and Verilog	2014-08-21 17:22:04 +02:00
Clifford Wolf	7bfc4ae120	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	2014-08-21 12:43:51 +02:00
Clifford Wolf	38addd4c67	Added support for global tasks and functions	2014-08-21 12:42:28 +02:00
Clifford Wolf	640d9fc551	Added "via_celltype" attribute on task/func	2014-08-18 14:29:30 +02:00
Clifford Wolf	6d56172c0d	Fixed line numbers when using here-doc macros	2014-08-14 22:26:30 +02:00
Clifford Wolf	f53984795d	Added support for non-standard """ macro bodies	2014-08-13 13:03:38 +02:00
Clifford Wolf	2dc3333734	Also allow "module foobar(input foo, output bar, ...);" syntax	2014-08-07 16:41:27 +02:00
Clifford Wolf	d259abbda2	Added AST_MULTIRANGE (arrays with more than 1 dimension)	2014-08-06 15:52:54 +02:00
Clifford Wolf	91dd87e60b	Improved scope resolution of local regs in Verilog+AST frontend	2014-08-05 12:15:53 +02:00
Clifford Wolf	b5a3419ac2	Added support for non-standard "module mod_name(...);" syntax	2014-08-04 15:40:07 +02:00
Clifford Wolf	1cb25c05b3	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	2014-07-31 13:19:47 +02:00
Clifford Wolf	7daad40ca4	Fixed counting verilog line numbers for "// synopsys translate_off" sections	2014-07-30 20:18:48 +02:00
Clifford Wolf	e605af8a49	Fixed Verilog pre-processor for files with no trailing newline	2014-07-29 20:14:25 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	b17d6531c8	Added "make PRETTY=1"	2014-07-24 17:15:01 +02:00
Clifford Wolf	ee8ad72fd9	fixed parsing of constant with comment between size and value	2014-07-02 06:27:04 +02:00
Clifford Wolf	0c4c79c4c6	Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)	2014-06-16 15:02:40 +02:00
Clifford Wolf	7f57bc8385	Improved parsing of large integer constants	2014-06-15 08:48:17 +02:00
Clifford Wolf	9bd7d5c468	Added handling of real-valued parameters/localparams	2014-06-14 12:00:47 +02:00
Clifford Wolf	7ef0da32cd	Added Verilog lexer and parser support for real values	2014-06-13 11:29:23 +02:00
Clifford Wolf	482d9208aa	Added read_verilog -sv options, added support for bit, logic, ... allways_ff, always_comb, and always_latch	2014-06-12 11:54:20 +02:00
Clifford Wolf	e275e8eef9	Add support for cell arrays	2014-06-07 11:48:50 +02:00
Clifford Wolf	5281562d0e	made the generate..endgenrate keywords optional	2014-06-06 23:05:01 +02:00
Clifford Wolf	b5cd7a0179	added while and repeat support to verilog parser	2014-06-06 17:40:04 +02:00
Clifford Wolf	f9c1cd5edb	Improved error message for options after front-end filename arguments	2014-06-04 09:10:50 +02:00
Clifford Wolf	7188542155	Fixed clang -Wdeprecated-register warnings	2014-04-20 14:28:23 +02:00
Clifford Wolf	a1be4816d6	Replaced depricated %name-prefix= bison directive	2014-04-20 14:22:11 +02:00