194 commits

Author	SHA1	Message	Date
Eddie Hung	7a3c403ba0	Missing close bracket	2019-06-15 09:10:01 -07:00
Eddie Hung	2ef2aa997c	read_aiger to not require clk_name for latches, plus debug	2019-06-15 09:07:53 -07:00
Eddie Hung	7876b5b8be	Cover __APPLE__ too for little to big endian	2019-06-14 12:40:51 -07:00
Eddie Hung	a48b5bfaa5	Further cleanup based on @daveshah1	2019-06-14 12:25:06 -07:00
Eddie Hung	97d2656375	Resolve comments from @daveshah1	2019-06-14 12:00:02 -07:00
Eddie Hung	a3be25ab0d	Cleanup	2019-06-14 10:27:30 -07:00
Eddie Hung	d005568f2e	Add TODO to parse_xaiger	2019-06-14 10:11:13 -07:00
Eddie Hung	bc22e2e3ee	Optimise some more	2019-06-13 17:02:58 -07:00
Eddie Hung	d09d4e0706	Move ConstEvalAig to aigerparse.cc	2019-06-13 16:28:11 -07:00
Eddie Hung	d39a5a77a9	Add ConstEvalAig specialised for AIGs	2019-06-13 13:13:48 -07:00
Eddie Hung	342fc0a600	parse_xaiger to cope with inouts	2019-06-12 15:45:46 -07:00
Eddie Hung	b21d29598a	Consistency	2019-06-12 09:40:51 -07:00
Eddie Hung	f7a9769c14	Merge remote-tracking branch 'origin/master' into xaig	2019-06-12 08:50:39 -07:00
Eddie Hung	2b350401c4	Fix spacing from spaces to tabs	2019-06-07 15:44:57 -07:00
Eddie Hung	6934f4bdd5	Fix spacing (entire file is wrong anyway, will fix later)	2019-06-07 11:30:36 -07:00
Eddie Hung	d00ae1d6a8	Remove unnecessary std::getline() for ASCII	2019-06-07 11:28:25 -07:00
Eddie Hung	a04521c6b7	Fix read_aiger -- create zero driver, fix init width, parse 'b'	2019-06-07 11:07:15 -07:00
Eddie Hung	7057753427	Rename label	2019-05-21 18:20:31 -07:00
Eddie Hung	b5a29460b9	Try again	2019-05-21 17:20:19 -07:00
Eddie Hung	1bff09f2ff	Fix warning	2019-05-21 16:26:20 -07:00
Eddie Hung	d9c915042a	Move clean from aigerparse to abc9	2019-04-23 13:42:35 -07:00
Eddie Hung	5f30a8795d	Tidy up	2019-04-22 17:47:05 -07:00
Eddie Hung	8f30019b68	Revert "Temporarily remove 'r' extension" ... This reverts commit eaf3c24772.	2019-04-22 17:41:21 -07:00
Eddie Hung	eaf3c24772	Temporarily remove 'r' extension	2019-04-22 11:54:19 -07:00
Eddie Hung	4883391b63	Merge remote-tracking branch 'origin/master' into xaig	2019-04-22 11:19:52 -07:00
Clifford Wolf	e158ea2097	Add log_debug() framework ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-22 17:25:52 +02:00
Eddie Hung	21701cc1df	read_aiger to parse 'r' extension	2019-04-18 17:39:36 -07:00
Eddie Hung	e1b550d203	Ignore a/i/o/h XAIGER extensions	2019-04-17 10:55:23 -07:00
Eddie Hung	fecafb2207	Forgot backslashes	2019-04-12 18:22:44 -07:00
Eddie Hung	9bfcd80063	Handle __dummy_o__ and __const[01]__ in read_aiger not abc	2019-04-12 18:21:16 -07:00
Eddie Hung	c776db3320	Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig	2019-04-12 17:09:24 -07:00
Eddie Hung	acf3f5694b	Fix inout handling for -map option	2019-04-12 17:02:24 -07:00
Eddie Hung	ada130b459	Also cope with duplicated CIs	2019-04-12 16:17:12 -07:00
Eddie Hung	1c6f0cffd9	Cope with an output having same name as an input (i.e. CO)	2019-04-12 12:27:07 -07:00
Eddie Hung	1a49cf29d8	parse_aiger() to rename all $lut cells after "clean"	2019-04-10 14:02:23 -07:00
Eddie Hung	36efec01b8	Fix spacing	2019-04-08 16:37:22 -07:00
Eddie Hung	bca3cf6843	Merge branch 'master' into xaig	2019-04-08 16:31:59 -07:00
Eddie Hung	3e89cf68bd	Add author name	2019-03-19 08:52:06 -07:00
Eddie Hung	da076344cc	parse_xaiger() to really pass single and multi-bit inout tests	2019-02-26 12:04:45 -08:00
Eddie Hung	8f02c846f6	parse_xaiger() to cope with multi bit inouts	2019-02-26 11:37:34 -08:00
Eddie Hung	316232a7dd	parse_xaiger() to untransform $inout.out output ports	2019-02-25 18:40:23 -08:00
Eddie Hung	721f6a14fb	read_aiger to accept empty string for clk_name, passable only if no latches	2019-02-25 15:34:02 -08:00
Eddie Hung	07036b8bf7	read_aiger to work with symbol table	2019-02-21 17:01:07 -08:00
Eddie Hung	085ed9f487	Add attribution	2019-02-21 14:40:13 -08:00
Eddie Hung	3307295488	Merge branch 'read_aiger' into xaig	2019-02-21 14:27:32 -08:00
Eddie Hung	9e299a0908	read_aiger to not do -purge for clean	2019-02-20 17:33:04 -08:00
Eddie Hung	32853b1f8d	lut/not/and suffix to be ${lut,not,and}	2019-02-20 16:30:30 -08:00
Eddie Hung	abc1c2672e	read_aiger to also rename 0 index lut when wideports	2019-02-20 16:17:22 -08:00
Eddie Hung	f9702a8abe	read_aiger: new naming fixes	2019-02-20 12:39:51 -08:00
Eddie Hung	83b66861e9	read_aiger to name wires with internal name, less likely to clash	2019-02-20 11:22:56 -08:00