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10974 commits

Author SHA1 Message Date
Marcelina Kościelnicka
055ba748bc backends/verilog: Add support for memory read port reset and init value. 2021-05-27 23:47:42 +02:00
Marcelina Kościelnicka
aabe1c382e backends/verilog: Add wide port support. 2021-05-27 16:15:46 +02:00
Marcelina Kościelnicka
1eae6025e7 memory_share: Improve same-address merging, recognize wide write ports. 2021-05-27 15:53:12 +02:00
Marcelina Kościelnicka
b019db1f37 kernel/mem: Add helpers for write port widening. 2021-05-27 14:32:51 +02:00
Marcelina Kościelnicka
83a218141c kernel/mem: Add sub_addr helpers. 2021-05-26 03:34:02 +02:00
Marcelina Kościelnicka
57ca51be76 kernel/mem: Add prepare_wr_merge helper. 2021-05-26 02:55:00 +02:00
Marcelina Kościelnicka
64ba3c3842 backends/verilog: Try to preserve mem write port priorities. 2021-05-26 00:19:31 +02:00
Marcelina Kościelnicka
d99fce3bc7 mem/extract_rdff: Fix "no FF made" edge case.
When converting a sync transparent read port with const address to async
read port, nothing at all needs to be done other than clk_enable change,
and thus we have no FF cell to return.  Handle this case correctly in
the helper and in its users.
2021-05-25 23:42:31 +02:00
Marcelina Kościelnicka
18806f1ef6 memory_bram: Reuse extract_rdff helper for make_outreg.
Also properly skip read ports with init value or reset when not making
use of make_outreg.  Proper support for matching those will land later.
2021-05-25 22:42:03 +02:00
Zachary Snow
0795b3ec07 verilog: fix case expression sign and width handling
- The case expression and case item expressions are extended to the
  maximum width among them, and are only interpreted as signed if all of
  them are signed
- Add overall width and sign detection for AST_CASE
- Add sign argument to genWidthRTLIL helper
- Coverage for both const and non-const case statements
2021-05-25 16:16:46 -04:00
Zachary Snow
15f35d6754 sv: support remaining assignment operators
- Add support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
- Unify existing support for: +=, -=, &=, |=, ^=
2021-05-25 16:15:57 -04:00
Marcelina Kościelnicka
3514c92dc4 mem/extract_rdff: Add alternate transparency handling.
When extracting read register from a transparent port that has an
enable, reset, or initial value, the usual trick of putting a register
on the address instead of data doesn't work.  In this case, create soft
transparency logic instead.

When transparency masks land, this will also be used to handle ports
that are transparent to only a subset of write ports.
2021-05-25 21:38:23 +02:00
Marcelina Kościelnicka
e6b078d156 opt_mem: Add reset/init value support. 2021-05-25 20:06:00 +02:00
Marcelina Kościelnicka
24b880b2de kernel/mem: Add model support for read port init value and resets.
Like wide port support, this is still completely unusable, and support
in various passes will be gradually added later.  It also has no support
at all in the cell library, so attempting to create a read port with
a reset or initial value will cause an assert failure for now.
2021-05-25 20:06:00 +02:00
Marcelina Kościelnicka
097de6c5f8 mem/extract_rdff: Fix wire naming and wide port support. 2021-05-25 17:51:47 +02:00
Marcelina Kościelnicka
96c7d60304 memory_bram: Respect write port priority. 2021-05-25 16:28:33 +02:00
Marcelina Kościelnicka
5628f5a88f opt_mem_feedback: Respect write port priority. 2021-05-25 15:59:41 +02:00
Marcelina Kościelnicka
4858721637 kernel/mem: Add emulate_priority helper. 2021-05-25 12:25:58 +02:00
Marcelina Kościelnicka
e0736c1622 Add memory_narrow pass. 2021-05-25 03:04:13 +02:00
Marcelina Kościelnicka
47f958ce45 memory_share: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka
9d5d5a48b1 opt_mem_feedback: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka
c1a4730739 memory_map: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka
1c903d3e47 sim: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka
69bf5c81c7 Reject wide ports in some passes that will never support them. 2021-05-25 02:07:25 +02:00
Marcelina Kościelnicka
35ee774ea8 kernel/mem: Add a Mem::narrow helper to split up wide ports. 2021-05-25 02:07:25 +02:00
Marcelina Kościelnicka
8c1999aac1 kernel/mem: Emit support for wide ports in packed mode.
Since the packed cell doesn't actually support wide ports yet, we just
auto-narrow them on emit.  The future packed cell will add
RD_WIDE_CONTINUATION and WR_WIDE_CONTINUATION parameters so the
transform will be trivially reversible for proper serialization.
2021-05-25 02:07:25 +02:00
Marcelina Kościelnicka
ff9713dd86 kernel/mem: Add model for wide ports.
Such ports cannot actually be created or used yet, this just adds the
necessary plumbing in the helper.  Subsequent commits will gradually
add wide port support to various yosys passes.
2021-05-25 02:07:25 +02:00
Marcelina Kościelnicka
95a39d3425 kernel/mem: Add priority_mask to model.
This is going to be used to store arbitrary priority masks in the
future.  Right now, it is not supported by our cell library, so the
priority_mask is computed from port order on helper construction,
and discarded when emitted.  However, this allows us to already convert
helper-using passes to the new model.
2021-05-25 00:38:20 +02:00
Marcelina Kościelnicka
835688bf80 opt_mem_feedback: Rewrite feedback path finding logic.
Fixes #2766.
2021-05-24 23:20:30 +02:00
Marcelina Kościelnicka
b706adb809 opt_mem_feedback: Convert to Mem helpers. 2021-05-24 23:20:30 +02:00
Marcelina Kościelnicka
dbfd0b61e3 hashlib: Add a hash for bool. 2021-05-24 22:02:15 +02:00
Marcelina Kościelnicka
5488c69d2a Add a .mailmap file. 2021-05-24 17:37:29 +02:00
Miodrag Milanović
c9dc7d5928
Merge pull request #2779 from YosysHQ/mwk/nuke-travis
Remove Travis CI.
2021-05-24 17:24:01 +02:00
Marcelina Kościelnicka
c3e65a4ce0 Remove Travis CI.
It has been replaced by GitHub Actions, and travis-ci.org is shutting
down in a few days anyway.
2021-05-24 17:18:03 +02:00
Marcelina Kościelnicka
b6721aa9d8 backend/firrtl: Convert to use Mem helpers. 2021-05-24 14:00:33 +02:00
Marcelina Kościelnicka
ef4ddfacf3 github actions: Test on several gcc and clang versions on Linux.
Fixes #2776.
2021-05-24 02:20:16 +02:00
Marcelina Kościelnicka
df2b79ca76 memory_share: Use Mem helpers. 2021-05-23 23:16:12 +02:00
Marcelina Kościelnicka
afd5366fc2 extract_rdff: Add initvals parameter.
This is not used yet, but will be needed when read port reset/initial
value support lands.
2021-05-23 22:05:26 +02:00
Marcelina Kościelnicka
33513d923a btor: Use is_mem_cell in one more place. 2021-05-23 20:34:52 +02:00
Marcelina Kościelnicka
d905990d01 memory_share: Split off feedback path finding as a separate pass.
memory_share is actually three passes in a trenchcoat.  Split off the
one that has the least in common with the other two as a separate pass.
2021-05-23 18:30:39 +02:00
Marcelina Kościelnicka
1eea06bcc0 Add new helper class for merging FFs into cells, use for memory_dff.
Fixes #1854.
2021-05-23 14:46:59 +02:00
Marcelina Kościelnicka
a23d9409e7 opt_mem: Remove write ports with const-0 EN.
Fixes #2765.
2021-05-23 14:30:56 +02:00
Marcelina Kościelnicka
039f4f48d5 memory_memx: Use Mem helper. 2021-05-22 22:31:07 +02:00
Marcelina Kościelnicka
c4cc888b2c kernel/rtlil: Extract some helpers for checking memory cell types.
There will soon be more (versioned) memory cells, so handle passes that
only care if a cell is memory-related by a simple helper call instead of
a hardcoded list.
2021-05-22 21:43:00 +02:00
Marcelina Kościelnicka
c7076495f1 kernel/mem: Add a check() function. 2021-05-22 21:42:53 +02:00
Marcelina Kościelnicka
ff9e0394b8 kernel/mem: defer port removal to emit() 2021-05-22 21:42:53 +02:00
Marcelina Kościelnicka
8c734e07b8 memory_dff: Use Mem helper. 2021-05-21 02:26:27 +02:00
Miodrag Milanović
9420bde09f
Run VS build on PRs and each push 2021-05-20 19:21:34 +02:00
Marcelina Kościelnicka
25de8faf10 Bump version 2021-05-20 12:50:32 +02:00
Marcelina Kościelnicka
4240498f71 tests/blif: Add missing gitignore 2021-05-20 12:49:51 +02:00