Claire Xenia Wolf
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72787f52fc
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Fixing old e-mail addresses and deadnames
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
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2021-06-08 00:39:36 +02:00 |
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Marcelina Kościelnicka
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aee439360b
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Add force_downto and force_upto wire attributes.
Fixes #2058.
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2020-05-19 01:42:40 +02:00 |
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Marcin Kościelnicki
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d48950d92d
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xilinx: Initial support for LUT4 devices.
Adds support for mapping logic, including LUTs, wide LUTs, and carry
chains.
Fixes #1547
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2020-02-07 09:03:22 +01:00 |
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Eddie Hung
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ce6a690d27
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xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
Now done in read_aiger
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2020-01-27 13:30:27 -08:00 |
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Marcin Kościelnicki
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7562e7304e
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xilinx: Use INV instead of LUT1 when applicable
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2019-11-25 20:40:39 +01:00 |
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Eddie Hung
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8e0a47fb92
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Really permute Xilinx LUT mappings as default LUT6.I5:A6
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2019-06-18 11:48:48 -07:00 |
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Eddie Hung
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8f5e6d73ff
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Revert "Fix (do not) permute LUT inputs, but permute mux selects"
This reverts commit da3d2eedd2.
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2019-06-18 11:35:21 -07:00 |
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Eddie Hung
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da3d2eedd2
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Fix (do not) permute LUT inputs, but permute mux selects
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2019-06-18 09:49:57 -07:00 |
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Eddie Hung
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608a95eb01
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Fix copy-pasta issue
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2019-06-17 22:29:22 -07:00 |
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Eddie Hung
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2a35c4ef94
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Permute INIT for +/xilinx/lut_map.v
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2019-06-17 22:24:35 -07:00 |
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Keith Rothman
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3090951d54
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Changes required for VPR place and route synth_xilinx.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-03-01 12:02:27 -08:00 |
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