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Author	SHA1	Message	Date
Clifford Wolf	3e0948e16f	Remove unneeded delays in smtbmc vlogtb	2017-07-03 15:37:17 +02:00
Clifford Wolf	287831dca3	Include output ports with constant driver in AIGER output	2017-07-03 14:53:17 +02:00
Clifford Wolf	ea805af6f5	Add "yosys-smtbmc --vlogtb-top"	2017-07-01 18:19:23 +02:00
Clifford Wolf	0a02cdb93b	Fix and_or_buffer optimization in opt_expr for signed operators	2017-07-01 16:05:26 +02:00
Clifford Wolf	7d2fb6e2fc	Fix smtbmc vlogtb bug in $anyseq handling	2017-07-01 02:13:32 +02:00
Clifford Wolf	0f217080cf	Add "design -import"	2017-06-30 19:18:52 +02:00
Clifford Wolf	8952bd6f45	Add chtype command	2017-06-30 17:57:34 +02:00
Clifford Wolf	18c030a8c9	Add $tribuf to opt_merge blacklist	2017-06-30 17:44:44 +02:00
Clifford Wolf	5b95901a1e	Merge pull request #353 from azonenberg/master ... greenpak4_counters: Use more human-readable names for inferred counters	2017-06-27 19:18:32 +02:00
Robert Ou	b102c0e254	coolrunner2: Add a few more primitives ... These cannot be inferred yet, but add them to cells_sim.v for now	2017-06-25 23:58:28 -07:00
Robert Ou	36b75dfcb7	coolrunner2: Initial mapping of latches	2017-06-25 23:58:28 -07:00
Robert Ou	4af5baab21	coolrunner2: Initial mapping of DFFs ... All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N (negative-edge triggered)	2017-06-25 23:58:28 -07:00
Robert Ou	1eb5dee799	coolrunner2: Remove redundant INVERT_PTC	2017-06-25 23:58:28 -07:00
Robert Ou	ffff001008	coolrunner2: Remove debug prints	2017-06-25 23:58:28 -07:00
Robert Ou	5798105d47	coolrunner2: Correctly handle $_NOT_ after $sop	2017-06-25 23:58:28 -07:00
Robert Ou	908ce3fdce	coolrunner2: Also construct the XOR cell in the macrocell	2017-06-25 23:58:28 -07:00
Robert Ou	a64b56648d	coolrunner2: Initial techmapping for $sop	2017-06-25 23:58:22 -07:00
Andrew Zonenberg	cbdddc3af9	greenpak4_counters: Changed generation of primitive names so that the absorbed register's name is included	2017-06-24 14:54:07 -07:00
Robert Ou	6e0fb889fa	coolrunner2: Initial commit	2017-06-24 07:22:56 -07:00
Clifford Wolf	155a80dfb7	Fix handling of init values in "abc -dff" and "abc -clk"	2017-06-20 15:32:23 +02:00
Clifford Wolf	1f517d2b96	Fix history namespace collision	2017-06-20 05:26:12 +02:00
Clifford Wolf	c0ca99483c	Store command history when terminating with an error	2017-06-20 04:41:58 +02:00
Clifford Wolf	f6421c83a2	Switched abc "clock domain not found" error to log_cmd_error()	2017-06-20 04:22:34 +02:00
Clifford Wolf	8f8baccfde	Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg"	2017-06-07 12:30:24 +02:00
Clifford Wolf	129984e115	Fix handling of Verilog ~& and ~| operators	2017-06-01 12:43:21 +02:00
Clifford Wolf	0290b68a44	Update ABC to hg rev efbf7f13ea9e	2017-05-31 11:55:37 +02:00
Clifford Wolf	e7a984a4df	Add dff2ff.v techmap file	2017-05-31 11:45:58 +02:00
Clifford Wolf	c365e33fd7	Fix AIGER back-end for multiple symbols per input/latch/output/property	2017-05-30 19:09:11 +02:00
Clifford Wolf	05df3dbee4	Add "setundef -anyseq"	2017-05-28 11:59:05 +02:00
Clifford Wolf	9ed4c9d710	Improve write_aiger handling of unconnected nets and constants	2017-05-28 11:31:35 +02:00
Clifford Wolf	d9201b85f3	Change default smt2 solver to yices (Yices 2 has switched its license to GPL)	2017-05-27 11:56:01 +02:00
Clifford Wolf	fad52abf70	Add aliases for common sets of gate types to "abc -g"	2017-05-24 11:39:05 +02:00
Clifford Wolf	dca3b3cd5f	Add examples/osu035	2017-05-23 18:38:20 +02:00
Clifford Wolf	664ba4d80e	Merge branch 'master' of github.com:cliffordwolf/yosys	2017-05-23 18:24:27 +02:00
Clifford Wolf	e0386d04f5	Merge pull request #346 from azonenberg/master ... greenpak4_counters: Added support for parallel output from GP_COUNTx cells	2017-05-23 14:07:30 +02:00
Andrew Zonenberg	184bd148c9	greenpak4_counters: Added support for parallel output from GP_COUNTx cells	2017-05-22 19:39:55 -07:00
Clifford Wolf	2122ae69b3	Add workaround for CBMC bug to SimpleC back-end	2017-05-17 21:07:54 +02:00
Clifford Wolf	662a047815	Enable readline and tcl in mxe builds	2017-05-17 20:46:22 +02:00
Clifford Wolf	6934b862d3	Add missing AndnotGate() and OrnotGate() declarations to rtlil.h	2017-05-17 19:10:57 +02:00
Clifford Wolf	05cdd58c8d	Add $_ANDNOT_ and $_ORNOT_ gates	2017-05-17 09:08:29 +02:00
Clifford Wolf	9f4fbc5e74	Add <modname>_init() function generator to simpleC back-end	2017-05-16 19:34:07 +02:00
Clifford Wolf	35be567605	Improve simplec back-end	2017-05-16 08:50:23 +02:00
Clifford Wolf	8d3c706459	Improve simplec back-end	2017-05-15 13:21:59 +02:00
Clifford Wolf	9c397ea78b	Improve simplec back-end	2017-05-14 13:14:49 +02:00
Clifford Wolf	628daab277	Improve simplec back-end	2017-05-13 18:47:31 +02:00
Clifford Wolf	ef7594ce3d	Improve simplec back-end	2017-05-12 22:39:16 +02:00
Clifford Wolf	7931e1ebb4	Added support for more gate types to simplec back-end	2017-05-12 17:42:31 +02:00
Clifford Wolf	bd4ed19887	Add first draft of simple C back-end	2017-05-12 14:13:33 +02:00
Clifford Wolf	241dc7dfb4	Update ABC to hg rev e79576e10d72	2017-05-11 10:32:32 +02:00
Clifford Wolf	1a4b7c6bfa	Fix boolector support in yosys-smtbmc	2017-05-08 14:33:22 +02:00