3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-28 19:35:53 +00:00
Commit graph

52 commits

Author SHA1 Message Date
Clifford Wolf
fd8c8d4fd3 Added FF cells to xilinx/cells_sim.v 2015-01-16 14:59:40 +01:00
Clifford Wolf
38dfc5c580 added minimalistic xilinx sim models 2015-01-08 00:05:11 +01:00