87 commits

Author	SHA1	Message	Date
Clifford Wolf	df3e6e1ec9	Remove some dead code from fsm_map	2017-08-21 15:02:16 +02:00
Larry Doolittle	2021ddecb3	Squelch trailing whitespace	2017-04-12 15:11:09 +02:00
Clifford Wolf	45e10c1c89	Be more conservative with merging large cells into FSMs	2017-01-26 09:19:28 +01:00
Clifford Wolf	49b8160488	Add warnings for quickly growing FSM table size in fsm_expand	2017-01-26 09:05:59 +01:00
Clifford Wolf	b63cace90f	Added support for fsm_encoding="user"	2016-11-02 13:15:49 +01:00
Clifford Wolf	0c8e973d32	Added "fsm_expand -full"	2016-11-02 09:31:39 +01:00
Clifford Wolf	d9d38eeedb	Bugfix in fsm_map for FSMs without reset state	2016-10-25 23:21:37 +02:00
Clifford Wolf	e92998a79c	Minor bugfix in FSM reset state detection	2016-07-12 09:46:15 +02:00
Clifford Wolf	b5a9fba0db	Further improved fsm_detect output, attempt to detect self-resetting circuits	2016-07-09 14:02:49 +02:00
Clifford Wolf	d63ffabacb	Added printing of some warning messages to fsm_detect	2016-07-09 13:23:06 +02:00
Clifford Wolf	0bc95f1e04	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00
Clifford Wolf	0d7fd2585e	Added "int ceil_log2(int)" function	2016-02-13 16:52:16 +01:00
Clifford Wolf	207736b4ee	Import more std:: stuff into Yosys namespace	2015-10-25 19:30:49 +01:00
Clifford Wolf	7f110e7018	renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()	2015-10-24 22:56:40 +02:00
Clifford Wolf	b66bf8bed1	Do not detect fsm state registers with init attribute	2015-09-21 11:54:00 +02:00
Clifford Wolf	b7535a6c75	Added $logic_not handling to fsm_detect	2015-09-18 10:46:50 +02:00
Clifford Wolf	246e362717	Bugfix in fsm_detect for complex muxtrees	2015-08-18 14:17:50 +02:00
Clifford Wolf	84bf862f7c	Spell check (by Larry Doolittle)	2015-08-14 10:56:05 +02:00
Clifford Wolf	766dd51447	Bugfix in fsm_extract	2015-07-03 18:42:36 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Clifford Wolf	f483dce7c2	Added $eq/$neq -> $logic_not/$reduce_bool optimization	2015-04-29 07:28:15 +02:00
Clifford Wolf	a038787c9b	Added onehot attribute	2015-02-04 18:52:54 +01:00
Clifford Wolf	bedd46338f	Added "fsm -encfile"	2015-01-30 22:46:53 +01:00
Clifford Wolf	a6c96b986b	Added Yosys::{dict,nodict,vector} container types	2014-12-26 10:53:21 +01:00
Clifford Wolf	edb3c9d0c4	Renamed extend() to extend_xx(), changed most users to extend_u0()	2014-12-24 09:51:17 +01:00
Clifford Wolf	fe829bdbdc	Added log_warning() API	2014-11-09 10:44:23 +01:00
William Speirs	e5b8390f44	Changed from "and" to "&&"	2014-10-15 00:59:22 +02:00
Clifford Wolf	35fbc0b35f	Do not the 'z' modifier in format string (another win32 fix)	2014-10-11 11:42:08 +02:00
Clifford Wolf	4569a747f8	Renamed SIZE() to GetSize() because of name collision on Win32	2014-10-10 17:07:24 +02:00
Clifford Wolf	f9a307a50b	namespace Yosys	2014-09-27 16:17:53 +02:00
Ruben Undheim	79cbf9067c	Corrected spelling mistakes found by lintian	2014-09-06 08:47:06 +02:00
Clifford Wolf	3a7d5d188d	Don't change existing binary FSM encoding if it is already optimal	2014-08-30 14:43:06 +02:00
Clifford Wolf	f910481f35	Using $pmux info in fsm_extract to optimize transition ctrl_in patterns	2014-08-30 14:34:49 +02:00
Clifford Wolf	ab019b0bd5	Improved handling of $pmux cells in fsm_extract	2014-08-30 14:11:57 +02:00
Clifford Wolf	7f734ecc09	Added module->uniquify()	2014-08-16 23:50:36 +02:00
Clifford Wolf	ca87116449	More idstring sort_by_* helpers and fixed tpl ordering in techmap	2014-08-15 02:40:46 +02:00
Clifford Wolf	13f2f36884	RIP $safe_pmux	2014-08-14 11:39:46 +02:00
Clifford Wolf	28cf48e31f	Some improvements in FSM mapping and recoding	2014-08-14 11:22:45 +02:00
Clifford Wolf	788bd02f97	Fixed FSM mapping for multiple reset-like signals	2014-08-10 12:04:02 +02:00
Clifford Wolf	2faef89738	Some improvements in fsm_opt and fsm_map for FSM with unreachable states	2014-08-09 14:49:51 +02:00
Clifford Wolf	58ac605470	Another fsm_extract bugfix	2014-08-08 14:56:04 +02:00
Clifford Wolf	7067c43ec0	Fixed "fsm -export"	2014-08-08 14:56:03 +02:00
Clifford Wolf	7c94024fc3	Fixed fsm_extract for wreduced muxes	2014-08-08 13:47:20 +02:00
Clifford Wolf	04727c7e0f	No implicit conversion from IdString to anything else	2014-08-02 18:58:40 +02:00
Clifford Wolf	b9bd22b8c8	More cleanups related to RTLIL::IdString usage	2014-08-02 13:19:57 +02:00
Clifford Wolf	cdae8abe16	Renamed port access function on RTLIL::Cell, added param access functions	2014-07-31 16:38:54 +02:00
Clifford Wolf	1cb25c05b3	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	2014-07-31 13:19:47 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	d878fcbdc7	Added log_cmd_error_expection	2014-07-27 12:05:50 +02:00
Clifford Wolf	10e5791c5e	Refactoring: Renamed RTLIL::Design::modules to modules_	2014-07-27 11:18:30 +02:00