Andrew Zonenberg
262f8f913c
greenpak4: Cleaned up trailing spaces in cells_sim
2016-12-14 14:14:45 +08:00
Andrew Zonenberg
c77e6e6114
greenpak4: Added GP_DCMPREF / GP_DCMPMUX
2016-12-14 14:14:26 +08:00
Clifford Wolf
00761de1b7
Bugfix in comment handling
2016-12-13 13:48:09 +01:00
Andrew Zonenberg
01d8278e53
Merge https://github.com/cliffordwolf/yosys
2016-12-12 17:05:06 +08:00
Clifford Wolf
a61c88f122
Added $anyconst support to AIGER back-end
2016-12-11 13:48:18 +01:00
Clifford Wolf
8a717ae1dc
Merge branch 'LSS-USP-unit-test-structure'
2016-12-11 11:03:25 +01:00
Clifford Wolf
71c47f13ed
Some minor CodingReadme changes in unit test section
2016-12-11 11:02:56 +01:00
Clifford Wolf
5c96982522
Build hotfix in tests/unit/Makefile
2016-12-11 10:58:49 +01:00
Andrew Zonenberg
c3c2983d12
Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF
2016-12-11 10:04:00 +08:00
rodrigosiqueira
b932e2355d
Improved unit test structure
...
Signed-off-by: rodrigosiqueira <rodrigosiqueiramelo@gmail.com>
Signed-off-by: chaws <18oliveira.charles@gmail.com>
* Merged run-all-unitest inside unit-test target
* Fixed Makefile dependencies
* Updated documentation about unit test
2016-12-10 18:21:56 -02:00
Andrew Zonenberg
8f3d1f8fcf
greenpak4: Added support for inferred input/output inverters on latches
2016-12-10 19:58:32 +08:00
Andrew Zonenberg
c53a33143e
greenpak4: Can now techmap inferred D latches (without set/reset or output inverter)
2016-12-10 18:46:36 +08:00
Andrew Zonenberg
797c03997e
greenpak4: Inverted D latch cells now have nQ instead of Q as output port name for consistency
2016-12-10 13:57:37 +08:00
Andrew Zonenberg
8767cdcac9
Added GP_DLATCH and GP_DLATCHI
2016-12-05 23:49:06 -08:00
Andrew Zonenberg
981f014301
Initial implementation of techlib support for GreenPAK latches. Instantiation only, no behavioral inference yet.
2016-12-05 21:22:41 -08:00
Andrew Zonenberg
e6ab00d419
Updated help text for synth_greenpak4
2016-12-05 20:11:37 -08:00
rodrigosiqueira
3f2f64f414
Added explanation about configure and create test
...
Added explanation about configure unit test environment and how to add new unit tests
2016-12-04 11:35:13 -02:00
rodrigosiqueira
e0152319f5
Added required structure to implement unit tests
...
Added modifications inside the main Makefile to refers the unit test Makefile.
Added separated Makefile only for compiling unit tests.
Added simple example of unit test.
Signed-off-by: Charles Oliveira <18oliveira.charles@gmail.com>
Signed-off-by: Pablo Alejandro <pabloabur@usp.br>
Signed-off-by: Rodrigo Siqueira <siqueira@ime.usp.br>
2016-12-04 11:34:27 -02:00
Clifford Wolf
a44cc7a3d1
Added $assert/$assume support to AIGER back-end
2016-12-03 13:20:29 +01:00
Clifford Wolf
37760541bd
Improved yosys-smtbmc default -t/--assume-skipped for --cex and --aig
2016-12-03 12:37:20 +01:00
Clifford Wolf
8a90e61c1a
Updated ABV to hg rev 8b555d9e67cf
2016-12-01 17:45:40 +01:00
Clifford Wolf
105b6374ae
Added examples/aiger/
2016-12-01 13:42:17 +01:00
Clifford Wolf
88b9733253
Added "yosys-smtbmc --aig"
2016-12-01 13:16:57 +01:00
Clifford Wolf
52c243cf05
Added support for partially initialized regs to smt2 back-end
2016-12-01 12:00:00 +01:00
Clifford Wolf
5fa1fa1e6f
Added "write_aiger -zinit -symbols -vmap"
2016-12-01 11:04:36 +01:00
Clifford Wolf
c1f762ca56
Added "write_aiger" command
2016-11-30 21:30:24 +01:00
Clifford Wolf
b1cdf772eb
Added "design -reset-vlog"
2016-11-30 11:25:55 +01:00
Clifford Wolf
ac7a175a3c
Improved equiv_purge log output
2016-11-29 13:30:35 +01:00
Clifford Wolf
df2e5aad6f
Bugfix in smt2 back-end for pure checker modules
2016-11-28 15:15:09 +01:00
Clifford Wolf
ecdc22b06c
Added support for macros as include file names
2016-11-28 14:50:17 +01:00
Clifford Wolf
c7f6fb6e17
Bugfix in "read_verilog -D NAME=VAL" handling
2016-11-28 14:45:05 +01:00
Clifford Wolf
c17d98f55c
Removed shebang line from smtio.py, fixes #279
2016-11-27 12:11:04 +01:00
Clifford Wolf
5c2c78e2dd
Added wire start_offset and upto handling BLIF back-end
2016-11-23 13:54:33 +01:00
Clifford Wolf
e444e59963
Added wire start_offset and upto handling to splitnets cmd
2016-11-23 13:54:33 +01:00
Clifford Wolf
73653de5ff
Merge pull request #274 from oldtopman/lcurses
...
Added optional flag for linking curses with readline.
2016-11-22 21:24:45 +01:00
Clifford Wolf
f257ccf22e
Added "yosys-smtbmc --append"
2016-11-22 21:21:13 +01:00
oldtopman
277f478572
Added optional flag for linking curses with readline.
2016-11-21 23:11:58 -07:00
Clifford Wolf
3b73d3f140
Merge pull request #272 from AlexDaniel/master
...
Markdownify README (№2)
2016-11-19 23:25:58 +01:00
Aleks-Daniel Jakimenko-Aleksejev
3c86da8000
Keep lines under 80 characters
...
Recent README changes added some characters to existing lines, which
made them longer than 80 characters. This commit fixes that.
2016-11-19 20:51:50 +02:00
Clifford Wolf
55785a96eb
Improved ABC default scripts
2016-11-19 18:20:54 +01:00
Aleks-Daniel Jakimenko-Aleksejev
751ad3c618
Markdownify README even further
2016-11-19 19:07:02 +02:00
Clifford Wolf
487b19b4fa
Merge pull request #271 from azidar/bugfix-assign-wmask
...
Bugfix: include assign to write-mask
2016-11-19 17:36:07 +01:00
Adam Izraelevitz
f77dc3bacc
Bugfix: include assign to write-mask
2016-11-18 11:49:26 -08:00
Clifford Wolf
e01382739d
More progress in FIRRTL back-end
2016-11-18 02:41:29 +01:00
Clifford Wolf
c051115e03
Progress in FIRRTL back-end
2016-11-18 00:32:35 +01:00
Clifford Wolf
57966a619f
Added first draft of FIRRTL back-end
2016-11-17 23:36:47 +01:00
Clifford Wolf
ce132cf652
Cleanups and fixed in write_verilog regarding reg init
2016-11-16 12:00:39 +01:00
Clifford Wolf
70d7a02cae
Added support for hierarchical defparams
2016-11-15 13:35:19 +01:00
Clifford Wolf
a926a6afc2
Remember global declarations and defines accross read_verilog calls
2016-11-15 12:42:43 +01:00
Clifford Wolf
a2206180d6
Merge pull request #268 from AlexDaniel/master
...
Markdownify README
2016-11-13 21:47:51 +01:00
