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Author SHA1 Message Date
Eddie Hung
0f1a4cc03c verific_import() changes to avoid ElaborateAll() 2019-05-03 20:53:25 +02:00
Clifford Wolf
373b236108
Merge pull request #969 from YosysHQ/clifford/pmgenstuff 
Improve pmgen, Add "peepopt" pass with shift-mul pattern
 2019-05-03 20:39:50 +02:00
Clifford Wolf
f170fb6383
Merge pull request #984 from YosysHQ/eddie/fix_982 
dffinit to do nothing when (* init *) value is 1'bx
 2019-05-03 20:34:32 +02:00
Eddie Hung
1d43a25f08 Revert "synth_xilinx to call dffinit with -noreinit" 
This reverts commit 1f62dc9081.
 2019-05-03 09:55:02 -07:00
Eddie Hung
e08df0c739 If init is 1'bx, do not add to dict as per @cliffordwolf 2019-05-03 08:06:16 -07:00
Eddie Hung
fc349de033 Revert "dffinit -noreinit to silently continue when init value is 1'bx" 
This reverts commit aa081f83c7.
 2019-05-03 08:05:37 -07:00
Clifford Wolf
71ede7cb05
Merge pull request #976 from YosysHQ/clifford/fix974 
Fix width detection of memory access with bit slice
 2019-05-03 15:29:44 +02:00
Clifford Wolf
97423cadda
Merge pull request #985 from YosysHQ/clifford/fix981 
Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires
 2019-05-03 15:25:46 +02:00
Clifford Wolf
d2aa123226 Fix typo in tests/svinterfaces/runone.sh 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-03 14:40:51 +02:00
Clifford Wolf
537b90ee88
Merge pull request #979 from jakobwenzel/svinterfacesTestcase 
fail svinterfaces testcases on yosys error exit
 2019-05-03 14:37:46 +02:00
Clifford Wolf
42190207b4 Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires, fixes #981 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-03 14:25:01 +02:00
Clifford Wolf
5c2c0b4bb2 Further improve unused-detection for opt_clean driver-driver conflict warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-03 09:22:26 +02:00
Clifford Wolf
f12e1155f1 Improve unused-detection for opt_clean driver-driver conflict warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-03 09:12:10 +02:00
Clifford Wolf
2b29aa5c86 Update pmgen documentation 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-03 08:35:45 +02:00
Clifford Wolf
e8c5afcb84 Fix typo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-03 08:25:30 +02:00
Eddie Hung
1f62dc9081 synth_xilinx to call dffinit with -noreinit 2019-05-02 17:41:20 -07:00
Eddie Hung
aa081f83c7 dffinit -noreinit to silently continue when init value is 1'bx 2019-05-02 17:40:39 -07:00
Udi Finkelstein
ac10e7d96d Initial implementation of elaboration system tasks 
(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
 2019-05-03 03:10:43 +03:00
Eddie Hung
283e33ba5a Trim off leading 1'bx in A 2019-05-02 16:02:37 -07:00
Eddie Hung
fc72f07efd Add don't care optimisation 2019-05-02 15:01:37 -07:00
Eddie Hung
d80445e049 Use new peepopt from #969 2019-05-02 11:35:57 -07:00
Eddie Hung
8829cba901 Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7mux 2019-05-02 11:25:34 -07:00
Eddie Hung
95867109ea Revert to pre-muxcover approach 2019-05-02 11:25:10 -07:00
Eddie Hung
d05ac7257e Missing help_mode 2019-05-02 11:14:28 -07:00
Eddie Hung
3b5e8c86a4 Fix -nocarry 2019-05-02 11:00:49 -07:00
Eddie Hung
5cd19b52da Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-02 10:44:59 -07:00
Jim Lawson
509f729e55 Merge remote-tracking branch 'upstream/master' 2019-05-02 07:59:07 -07:00
Jakob Wenzel
98ffe5fb00 fail svinterfaces testcases on yosys error exit 2019-05-02 09:52:30 +02:00
Clifford Wolf
98925f6c4b
Merge pull request #963 from YosysHQ/eddie/synth_xilinx_fine 
Revert synth_xilinx 'fine' label more to how it used to be...
 2019-05-02 09:11:07 +02:00
Eddie Hung
485bf372e7
Merge pull request #978 from ucb-bar/fmtfirrtl 
Re-indent firrtl.cc:struct memory - no functional change.
 2019-05-01 18:24:21 -07:00
Eddie Hung
d394b9301b Back to passing all xc7srl tests! 2019-05-01 18:23:21 -07:00
Eddie Hung
31ff0d8ef5 Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine 2019-05-01 18:09:38 -07:00
Eddie Hung
f86d153cef Merge branch 'master' of github.com:YosysHQ/yosys 2019-05-01 16:26:43 -07:00
Jim Lawson
6ea09caf01 Re-indent firrtl.cc:struct memory - no functional change. 2019-05-01 16:21:13 -07:00
Jim Lawson
6c361bb198 Merge remote-tracking branch 'upstream/master' 2019-05-01 16:13:11 -07:00
Clifford Wolf
7a0af004a0 Merge branch 'clifford/fix883' 2019-05-02 00:04:12 +02:00
Clifford Wolf
521663f09e Add missing enable_undef to "sat -tempinduct-def", fixes #883 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-02 00:03:31 +02:00
Clifford Wolf
e8a157b47c
Merge pull request #977 from ucb-bar/fixfirrtlmem 
Fix #938 - Crash occurs in case when use write_firrtl command
 2019-05-01 23:47:16 +02:00
Jim Lawson
38f5424f92 Fix #938 - Crash occurs in case when use write_firrtl command 
Add missing memory initialization.
Sanity-check memory parameters.
Add Cell pointer to memory object (for error reporting).
 2019-05-01 13:16:01 -07:00
Clifford Wolf
93b7fd7744 Fix floating point exception in qwp, fixes #923 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 15:06:46 +02:00
Clifford Wolf
6bbe2fdbf3 Add splitcmplxassign test case and silence splitcmplxassign warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 10:01:54 +02:00
Clifford Wolf
3b6a02d3a7 Fix width detection of memory access with bit slice, fixes #974 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 09:57:26 +02:00
Clifford Wolf
e5cb9435a0 Add additional test cases for for-loops 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 09:32:07 +02:00
Clifford Wolf
a30b99e66e Silently resolve completely unused cell-vs-const driver-driver conflicts 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 09:29:34 +02:00
Clifford Wolf
59d74a3348 Re-enable "final loop assignment" feature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 09:02:39 +02:00
Clifford Wolf
32ff37bb5a Fix segfault in wreduce 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 22:20:45 +02:00
Jim Lawson
58650ffe87 Merge remote-tracking branch 'upstream/master' 2019-04-30 13:19:27 -07:00
Clifford Wolf
e35fe1344d Disabled "final loop assignment" feature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 20:22:50 +02:00
Clifford Wolf
9c7d23446d
Merge pull request #972 from YosysHQ/clifford/fix968 
Add final loop variable assignment when unrolling for-loops
 2019-04-30 18:09:44 +02:00
Clifford Wolf
a27eeff573
Merge pull request #966 from YosysHQ/clifford/fix956 
Drive dangling wires with init attr with their init value
 2019-04-30 18:08:41 +02:00