mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-04-19 18:33:36 +00:00
Code Activity
15952 commits 132 branches 66 tags 57 MiB
Commit graph

1 commit

Author SHA1 Message Date
Zachary Snow
c18ddbcd82 verilog: impose limit on maximum expression width 
Designs with unreasonably wide expressions would previously get stuck
allocating memory forever.
 2021-03-04 15:20:52 -05:00