YRabbit
64700dec65
Gowin. Disable unsupported BSRAM mode in GW5A
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All supported (and planned to be supported) GW5A series chips do not
support the 2: Read-before-Write write mode.
Here, we prohibit the generation of BSRAM with this mode.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-10-23 09:59:56 +01:00
Miodrag Milanović
2613c1c0a9
Merge pull request #5438 from cr1901/posix-bugpoint
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Add sys/wait.h header to bugpoint to bring in constants.
2025-10-22 12:40:26 +02:00
github-actions[bot]
37875fdedf
Bump version
2025-10-21 00:23:46 +00:00
William D. Jones
311a2739f6
Add sys/wait.h header to bugpoint to bring in constants.
2025-10-20 19:50:18 -04:00
Jannis Harder
f6fb423ee8
Merge pull request #5430 from YosysHQ/micko/sim_cycle_width
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sim: Make cycle width small as possible and configurable
2025-10-20 18:51:32 +02:00
Jannis Harder
6a0ee6e4fb
Revert sim's cycle_width default back to 10, but keep -width option
2025-10-20 14:40:05 +02:00
github-actions[bot]
1598771a37
Bump version
2025-10-19 00:26:17 +00:00
Mohamed Gaber
b510c36162
hotfix: headers mistakenly added to clean target
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- fix `make clean` deleting a number of headers when ENABLE_PYOSYS is set to 1
2025-10-18 14:08:20 +01:00
github-actions[bot]
272aa9cde2
Bump version
2025-10-17 00:23:40 +00:00
Maxim Kudinov
6535995005
synth_gowin: fix help hint style
2025-10-16 11:09:28 +01:00
Maxim Kudinov
8c347826f6
synth_gowin: make help description more clear
2025-10-16 11:09:28 +01:00
Maxim Kudinov
8f6d63c082
synth_gowin: make setundef an off by default option
2025-10-16 11:09:28 +01:00
Miodrag Milanovic
f11a61b32b
sim: Make cycle width small as possible and configurable
2025-10-16 11:37:44 +02:00
Miodrag Milanovic
db8c1878a0
fix dlopen using fs:path with mingw
2025-10-16 08:30:43 +02:00
github-actions[bot]
061b6ce2ad
Bump version
2025-10-16 00:23:57 +00:00
Miodrag Milanović
759996b968
Merge pull request #5427 from donn/plugin_search_paths
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plugins: add search paths
2025-10-15 20:02:05 +02:00
Emil J
9d21585a4c
Merge pull request #5426 from rocallahan/parse-sigspec
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Don't stop parsing sigspec after a {} group.
2025-10-15 17:31:11 +02:00
Mohamed Gaber
dce70abd94
plugins: support Windows path delimiters
2025-10-15 15:53:44 +03:00
Mohamed Gaber
e86797f029
plugins: add search path
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This uses the environment variable `YOSYS_PLUGIN_PATH` to provide multiple colon-delimited search paths for native plugins in a similar manner to `PATH` for executables and `PYTHONPATH` for Python modules.
This addresses https://github.com/YosysHQ/yosys/issues/2545 , allowing Yosys to be better packaged in non-FHS environments such as Nix.
2025-10-15 14:13:25 +03:00
github-actions[bot]
4970ad5a18
Bump version
2025-10-15 00:23:49 +00:00
Robert O'Callahan
e099a7d34a
Don't stop parsing sigspec after a {} group.
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Resolves #5424
2025-10-14 21:18:58 +00:00
Krystine Sherwin
c599d6a67e
tests/svinterfaces: re-chmod test script
2025-10-15 09:49:53 +13:00
Krystine Sherwin
10a55119a9
hierarchy.cc: Tidying
2025-10-15 09:42:47 +13:00
Krystine Sherwin
5d2d544109
hierarchy.cc: Don't segfault
2025-10-15 09:38:43 +13:00
Krystine Sherwin
37ba29482e
docs: Amend modports support to all SVI
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Also some formatting fixes.
2025-10-15 09:17:52 +13:00
Krystine Sherwin
7bb0a1913e
hierarchy.cc: Raise error on positional interface
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Add test to check that it does error.
2025-10-15 09:10:33 +13:00
Miodrag Milanović
2e3bfca294
Merge pull request #5419 from YosysHQ/micko/verific_fix_nocolumns
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verific: Fix error compiling without VERIFIC_LINEFILE_INCLUDES_COLUMNS
2025-10-14 17:05:31 +02:00
Miodrag Milanović
a89c5b97d8
Merge pull request #5423 from YosysHQ/update_abc
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Update abc
2025-10-14 17:05:13 +02:00
Emil J
a5960ce515
Merge pull request #5197 from YosysHQ/emil/opensta-verilog-export
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OpenSTA verilog compatibility
2025-10-14 16:46:37 +02:00
Miodrag Milanovic
7d2857b30f
Fix regex checks
2025-10-14 16:04:56 +02:00
N. Engelhardt
4513783a02
add tests
2025-10-14 15:48:16 +02:00
Krystine Sherwin
1eb5181700
Add tests/verilog/local_include.*
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`read_verilog` supports checking both the current directory and the source directory for relative includes. Make sure we aren't regressing that.
2025-10-14 15:47:08 +02:00
Emil Jiří Tywoniak
d1a628ab26
CI: bump WASI SDK from 19 to 27
2025-10-14 15:47:08 +02:00
Emil Jiří Tywoniak
79cd4e08c4
io: use std::filesystem
2025-10-14 15:47:07 +02:00
Emil J. Tywoniak
5cfe6a9c1e
reduce OS ifdefs, refactor getting dirs and filenames from paths to files
2025-10-14 15:46:17 +02:00
Emil J. Tywoniak
e9aedf505c
chtype: replace publish pass with chtype -publish_icells
2025-10-14 15:01:48 +02:00
Miodrag Milanovic
d92cf2f5b0
Compile abc when submodule updates
2025-10-14 14:54:56 +02:00
Miodrag Milanovic
d3d3a9f1ea
Update ABC
2025-10-14 14:47:17 +02:00
Emil J
109abd3224
Merge pull request #5421 from YosysHQ/emil/sort-pass
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sort: init
2025-10-14 10:51:25 +02:00
Krystine Sherwin
bbceaa6b5e
docs: Note partial support of modports
2025-10-14 14:59:32 +13:00
github-actions[bot]
25f2a88770
Bump version
2025-10-14 00:22:29 +00:00
Emil J. Tywoniak
e5edd2acdb
sort: init
2025-10-13 17:32:26 +02:00
Emil J
71eadc9ab5
Merge pull request #5418 from yrabbit/gw5-dff-and-memory
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Gowin. Reduce the range of flip-flop types.
2025-10-13 17:26:56 +02:00
Emil J. Tywoniak
c46df9ffdc
box_derive: rename -apply to -apply_derived_type
2025-10-13 17:24:32 +02:00
Emil J. Tywoniak
d7cea2c35c
box_derive: add -apply
2025-10-13 17:24:32 +02:00
Emil J. Tywoniak
7d8f92e198
publish: add pass for renaming private cell types to public
2025-10-13 17:24:32 +02:00
Jannis Harder
84b5ec856e
Merge pull request #4320 from YosysHQ/ywb_asserts
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write_btor: Include `$assert` and `$assume` cells in -ywmap output
2025-10-13 15:30:11 +02:00
Miodrag Milanovic
1f11b2c529
verific: Add src to message missed in #5406
2025-10-13 15:16:17 +02:00
Miodrag Milanovic
dc959cdf4a
verific: Fix error compiling without VERIFIC_LINEFILE_INCLUDES_COLUMNS
2025-10-13 15:16:17 +02:00
Miodrag Milanovic
9570b39519
verifix: fix bits() deprecation warnings
2025-10-13 09:57:22 +02:00
