7 commits

Author	SHA1	Message	Date
Clifford Wolf	e6d33513a5	Added module->design and cell->module, wire->module pointers	2014-07-31 14:11:39 +02:00
Clifford Wolf	1cb25c05b3	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	2014-07-31 13:19:47 +02:00
Clifford Wolf	10e5791c5e	Refactoring: Renamed RTLIL::Design::modules to modules_	2014-07-27 11:18:30 +02:00
Clifford Wolf	483c99fe46	Added "design -push" and "design -pop"	2014-02-20 23:28:59 +01:00
Clifford Wolf	366dcd3abf	Fixed use of "cmd_error" in passes/cmds/design.cc	2014-02-07 14:16:42 +01:00
Clifford Wolf	cf593222f2	Added design -stash/-copy-from/-copy-to	2014-02-06 21:52:07 +01:00
Clifford Wolf	0f38008ed3	Added "design" command (-reset, -save, -load)	2013-07-27 14:27:51 +02:00