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Author	SHA1	Message	Date
Clifford Wolf	e5d42ebb4d	Added $display %m support, fixed mem leak in $display, fixes #128	2016-03-19 11:51:13 +01:00
Clifford Wolf	ff5c61b120	Added black box modules for all the 7-series design elements (as listed in ug953)	2016-03-19 11:09:10 +01:00
Clifford Wolf	ef4207d5ad	Fixed localparam signdness, fixes #127	2016-03-18 12:15:00 +01:00
Clifford Wolf	b6d08f39ba	Set "nosync" attribute on internal task/function wires	2016-03-18 10:53:29 +01:00
Clifford Wolf	33c10350b2	Fixed Verilog parser fix and more similar improvements	2016-03-15 12:22:31 +01:00
Andrew Becker	81d4e9e7c1	Use left-recursive rule for cell_port_list in Verilog parser.	2016-03-15 12:03:40 +01:00
Clifford Wolf	2a8d5e64f5	Bugfix in write_verilog for RTLIL processes	2016-03-14 13:03:28 +01:00
Clifford Wolf	dac807fb33	Cleanups and improvements in examples/cmos/	2016-03-11 11:30:01 +01:00
Clifford Wolf	3265795154	Merge commit 'b34385ec92'	2016-03-11 11:10:44 +01:00
Clifford Wolf	35a6ad4cc1	Fixed typos in verilog_defaults help message	2016-03-10 11:14:51 +01:00
Clifford Wolf	d117893007	Added "write_edif -nogndvcc"	2016-03-08 21:30:45 +01:00
Clifford Wolf	dcd4fb9984	Added examples/cxx-api/evaldemo.cc	2016-03-08 16:54:15 +01:00
Clifford Wolf	e7ed653771	Merge branch 'master' of github.com:cliffordwolf/yosys	2016-03-07 11:17:44 +01:00
Clifford Wolf	c4aaed099f	Using "mfs" and "lutpack" in ABC lut mapping	2016-03-07 11:14:11 +01:00
Uros Platise	b34385ec92	Completed ngspice digital example with verilog tb	2016-03-05 08:34:05 +01:00
Clifford Wolf	b0ac32bc03	Added digital (xspice) example code to examples/cmos/	2016-03-02 12:07:57 +01:00
Clifford Wolf	5547fae4cf	Be more conservative with net names in spice output	2016-03-02 12:02:59 +01:00
Clifford Wolf	b36cad75f6	Merge pull request #119 from SebKuzminsky/spelling-fixes ... user-facing spelling fixes	2016-02-29 10:18:50 +01:00
Sebastian Kuzminsky	7e6426a67d	user-facing spelling fixes ... "speciefied" -> "specified" "unkown" -> "unknown"	2016-02-28 15:14:01 -07:00
Clifford Wolf	c89f61c730	We are now in 0.6+ development	2016-02-26 17:24:31 +01:00
Clifford Wolf	5869d26da0	Yosys 0.6	2016-02-26 16:55:21 +01:00
Clifford Wolf	22c549ab37	Fixed BLIF parser for empty port assignments	2016-02-24 09:16:43 +01:00
Clifford Wolf	45af4a4acf	Use easyer-to-read unoptimized ceil_log2() ... see here for details on the optimized version: http://svn.clifford.at/handicraft/2016/esbmc/ceilog2.c	2016-02-15 23:06:18 +01:00
Clifford Wolf	7a9257e7b5	Updated ABC to ae7d65e71adc	2016-02-15 15:30:46 +01:00
Clifford Wolf	85fe6d176f	Updated command reference in manual	2016-02-14 11:02:11 +01:00
Clifford Wolf	0761ad6e18	Changelog for upcoming 0.6 release	2016-02-14 10:50:19 +01:00
Clifford Wolf	0c4b311242	Fixed more visual studio warnings	2016-02-14 09:35:25 +01:00
Clifford Wolf	bcc873b805	Fixed some visual studio warnings	2016-02-13 17:31:24 +01:00
Clifford Wolf	6f1d694171	Merge branch 'master' of github.com:cliffordwolf/yosys	2016-02-13 17:01:29 +01:00
Clifford Wolf	0d7fd2585e	Added "int ceil_log2(int)" function	2016-02-13 16:52:16 +01:00
Clifford Wolf	0373bd98bb	Fixed MXE ABC build	2016-02-13 15:43:23 +01:00
Clifford Wolf	a75f94ec4a	Run dffsr2dff in synth_xilinx	2016-02-13 08:20:19 +01:00
Clifford Wolf	7bd329afa0	Support for more Verific primitives (patch I got per email)	2016-02-13 08:19:30 +01:00
Clifford Wolf	840a6dc893	Updated ABC	2016-02-08 01:13:53 +01:00
Clifford Wolf	0ccfb88728	Work around DDR dout sim glitches in ice40 SB_IO sim model	2016-02-07 11:19:48 +01:00
Clifford Wolf	e7bec9bbb8	Updated ABC	2016-02-07 08:56:32 +01:00
Clifford Wolf	825b99efc1	Added "stat -liberty" for calculating chip area	2016-02-04 12:26:13 +01:00
Clifford Wolf	6a27cbe5b1	Bugfix in Verific front-end	2016-02-03 08:59:57 +01:00
Clifford Wolf	4a3e1ded1e	Updated verific build instructions	2016-02-02 19:50:17 +01:00
Clifford Wolf	801c022457	Improved dffsr2dff pass	2016-02-02 19:42:49 +01:00
Clifford Wolf	d69395ca08	Added dffsr2dff	2016-02-02 17:19:01 +01:00
Clifford Wolf	ba407da187	Added addBufGate module method	2016-02-02 11:26:07 +01:00
Clifford Wolf	d6592d5b99	Use alphanumerical order instead of idstring idx in opt_clean compare_signals()	2016-02-02 09:16:18 +01:00
Clifford Wolf	74657f88a1	Added CodeOfConduct	2016-02-01 16:36:59 +01:00
Clifford Wolf	7ef613ebdf	Updated ABC to hg rev ee212a9e94df	2016-02-01 15:51:27 +01:00
Clifford Wolf	bd10927f45	Progress in cell library documentation	2016-02-01 13:58:10 +01:00
Clifford Wolf	17372d8abd	Added "abc -luts" option, Improved Xilinx logic mapping	2016-02-01 12:40:32 +01:00
Clifford Wolf	9251553592	Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)	2016-02-01 11:49:11 +01:00
Clifford Wolf	01bcc5663f	SigMap performance improvement	2016-02-01 10:10:20 +01:00
Clifford Wolf	ea492abcf0	hashlib mfp<> performance improvements	2016-02-01 10:03:03 +01:00