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Code Activity
17709 commits 138 branches 70 tags 85 MiB
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2224 commits

Author SHA1 Message Date
Emil J. Tywoniak
3d2e268154 kernel: add SwitchRule signal_src 
(cherry picked from commit 53585db9f7)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
b2d57e5d41 rtlil: add case_src to CaseRule 
(cherry picked from commit a217a5c716)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
6f3b384ac4 rtlil: add source tracking to CaseRule actions 
(cherry picked from commit c36370f227)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
dad4961221 rtlil: replace SigSig actions with new type SyncAction 
(cherry picked from commit 94a53e08bc)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
bbfadc27a1 twines phase-3 build fix: post-fork main files broken by twine migration 
kernel/compressor_tree.cc, passes/tests/test_kogge_stone.cc,
passes/opt/peepopt_shiftpow2.pmg, and techlibs/lattice/lattice_dsp_nexus.pmg
(plus the 5 new constids it needs: A0, B0, PIPELINED, SIGNED, SUBTRACT)
were all added to main after the emil/twines-proc-srcloc fork point, so no
commit in this phase's range ever touches them. They still use the old
IdString-based addWire/addCell/setPort/getParam APIs (NEW_ID, plain \X
port names) that the twine migration replaces, so they fail to build
against current HEAD. Not attributable to any single commit in this
phase per task.md's carve-out for genuinely phase-spanning fixes -
bundled here as its own commit rather than folded into an unrelated
pick.
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
fd1d75122d patch: fix signorm commit broken by twine rename 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
9552cba923 rtlil: options for dumping twines 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
ec1149a68a functinoal: twines 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
92b16718c9 twine: fix replayability, reduce TwineSearch usage 2026-07-20 13:57:10 +02:00
Emil J. Tywoniak
fb4f567456 twine: auto type WIP 2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
3bfc7228f3 signorm: discard newly_driven capacity for performance 2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
93ea3dfd4b rtlil: fix twine handling 2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
31c264a433 twine: switch to std::deque from forked plf::colony 2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
c08fb7f3ed WIP migration to twine 2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
65f35a88eb WIP migration to twine 2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
edf551bad4 newcelltypes: twines 2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
bb8eee6e93 ff: twines 2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
0f884b6cba twine: avoid TwinePool::lookup 2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
171eddf5c3 twine: GC again 2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
6d89534418 prevent IdString construction when looking up module from instance type 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
a9a190f70f twine: GC again WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
c8e42bc15b twine: fix another off-by-one 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
94f347a71c twine: fix off-by-one static twine error 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
a5248849d9 WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
b01a3694f0 WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
77ad54139e WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
e952044215 WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
7422b71802 WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
1210d8e117 WIP 2026-07-20 12:27:02 +02:00
Emil J. Tywoniak
6cd77a9af6 twine: start indexable colony with integer indices including preallocated twines 2026-07-20 12:27:02 +02:00
Emil J. Tywoniak
399cf1f970 BROKEN 2026-07-20 12:27:02 +02:00
Emil J. Tywoniak
30bc1c23ee WIP 2026-07-20 12:27:02 +02:00
Emil J. Tywoniak
10436f31cd WIP 2026-07-20 12:27:02 +02:00
Emil J. Tywoniak
f508244f36 rtlil: fix masquerade 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
edb43b93d7 rtlil: introduce ModuleNameMasq (KNOWN BROKEN, do not merge) 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
3da81b2e9d rtlil: Module::clone attaches to source design; callers use clone(dst) 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
be4d67d1a3 rtlil: replace AttrObject::meta_idx_ with ObjMeta pointer 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
301fc0a6a7 Patch: route staged cell names through per-Patch dict 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
84c6c61736 rtlil: extend per-Design meta vector to hold name slot 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
d7f88dd3a0 rtlil: evacuate src_id_ from AttrObject to per-Design meta vector 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
0bff07d55c rtlil: add Module* back-pointer to RTLIL::Memory 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
d37581d9d7 rtlil: add per-Design src meta vector + freelist 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
452964e75a rtlil: add Module* back-pointer to inner-process AttrObjects 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
f017bb8a93 twine 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
dacfded6d5 memory_map: propagate Mem src onto every generated cell 2026-07-17 23:49:06 +02:00
Emil J. Tywoniak
9cebc6e412 patch: split into single-output patch + multi-output patch_ports; drop input-cone gc 2026-07-17 23:49:06 +02:00
Emil J. Tywoniak
aab3ab7cf4 patch: gc collects src from every removed cell; ff.cc routes through Patch 2026-07-17 23:49:06 +02:00
Emil J. Tywoniak
f977f3e9ad patch: merge src into existing cells; opt_merge/_inc + onehot + ff.cc use Patch 2026-07-17 23:49:06 +02:00
Emil J. Tywoniak
19b6338e52 utils: add BitGrouper for shared bit-partition logic 2026-07-17 23:49:06 +02:00
Emil J. Tywoniak
738b46941a opt_expr: convert remaining rewrites to patcher 2026-07-17 23:49:06 +02:00