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Author	SHA1	Message	Date
R. Ou	a6aeee4e1a	coolrunner2: Insert many more required feedthrough cells	2020-03-01 16:56:21 -08:00
Eddie Hung	69c2d3848a	Merge pull request #1727 from YosysHQ/eddie/fix_write_smt2 ... ystests: fix write_smt2_write_smt2_cyclic_dependency_fail	2020-02-29 08:15:24 -08:00
Eddie Hung	de3e5fcdc6	ystests: fix write_smt2_write_smt2_cyclic_dependency_fail	2020-02-28 12:33:55 -08:00
Eddie Hung	b741954461	Merge pull request #1726 from YosysHQ/eddie/fix1710 ... ast: fixes #1710; do not generate RTLIL for unreachable ternary branch	2020-02-28 10:39:03 -08:00
Dan Ravensloft	d7987fec12	Add -flowmap to synth and synth_ice40	2020-02-28 14:29:57 +00:00
Eddie Hung	5bba9c3640	ast: fixes #1710; do not generate RTLIL for unreachable ternary	2020-02-27 16:55:55 -08:00
Eddie Hung	825b96fdcf	Comment out log()	2020-02-27 16:53:49 -08:00
Eddie Hung	090e54569a	Remove RAMB{18,36}E1 from cells_xtra.py	2020-02-27 10:33:04 -08:00
Eddie Hung	0f4c1906bb	Small fixes	2020-02-27 10:29:53 -08:00
Eddie Hung	78929e8c3d	Fixes for older compilers	2020-02-27 10:17:29 -08:00
Eddie Hung	a179d918ec	Revert "Fix tests/arch/xilinx/fsm.ys to count flops only" ... This reverts commit 68f903c6dd7403a4cf280cf71ee02d20345938b5.	2020-02-27 10:17:29 -08:00
Eddie Hung	e79376d6cb	ast: quiet down when deriving blackbox modules	2020-02-27 10:17:29 -08:00
Eddie Hung	88d5997c80	abc9_ops: suppress -prep_box warning for abc9_flop	2020-02-27 10:17:29 -08:00
Eddie Hung	376319dc8d	xilinx: Update RAMB* specify entries	2020-02-27 10:17:29 -08:00
Eddie Hung	6bd9550100	ice40: add delays to SB_CARRY	2020-02-27 10:17:29 -08:00
Eddie Hung	3b74e0fa45	xilinx: add delays to INV	2020-02-27 10:17:29 -08:00
Eddie Hung	6bb3d9f9c0	Make TimingInfo::TimingInfo(SigBit) constructor explicit	2020-02-27 10:17:29 -08:00
Eddie Hung	9dcf204dec	TimingInfo: index by (port_name,offset)	2020-02-27 10:17:29 -08:00
Eddie Hung	7c3b4b80ea	Fix spacing	2020-02-27 10:17:29 -08:00
Eddie Hung	aa969f8778	More +/ice40/cells_sim.v fixes	2020-02-27 10:17:29 -08:00
Eddie Hung	f858219c4e	Cleanup tests	2020-02-27 10:17:29 -08:00
Eddie Hung	717fb492b3	Update bug1630.ys to use -lut 4 instead of lut file	2020-02-27 10:17:29 -08:00
Eddie Hung	b0ffd9cd8b	Make +/xilinx/cells_sim.v legal	2020-02-27 10:17:29 -08:00
Eddie Hung	d6cff77751	abc9_ops: still emit delay table even box has no timing	2020-02-27 10:17:29 -08:00
Eddie Hung	5ff60d2057	write_xaiger: add comment about arrival times of flop outputs	2020-02-27 10:17:29 -08:00
Eddie Hung	683c5ce940	abc9_ops: demote lack of box timing info to warning	2020-02-27 10:17:29 -08:00
Eddie Hung	1ef1ca812b	Get rid of (* abc9_{arrival,required} *) entirely	2020-02-27 10:17:29 -08:00
Eddie Hung	a6fec9fe60	abc9_ops: use TimingInfo for -prep_{lut,box} too	2020-02-27 10:17:29 -08:00
Eddie Hung	3ea5506f81	abc9_ops: use TimingInfo for -prep_{lut,box} too	2020-02-27 10:17:29 -08:00
Eddie Hung	cda4acb544	abc9_ops: add and use new TimingInfo struct	2020-02-27 10:17:29 -08:00
Eddie Hung	bc97e64b21	Fix tests/arch/xilinx/fsm.ys to count flops only	2020-02-27 10:17:29 -08:00
Eddie Hung	7d86aceee3	Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy	2020-02-27 10:17:29 -08:00
Eddie Hung	3728ef1765	ice40: fix specify for inverted clocks	2020-02-27 10:17:29 -08:00
Eddie Hung	aac309626b	Fix tests by gating some specify constructs from iverilog	2020-02-27 10:17:29 -08:00
Eddie Hung	977262c803	Update simple_abc9 tests	2020-02-27 10:17:29 -08:00
Eddie Hung	e22fee6cdd	abc9_ops: ignore (* abc9_flop *) if not '-dff'	2020-02-27 10:17:29 -08:00
Eddie Hung	a76520112d	ice40: specify fixes	2020-02-27 10:17:29 -08:00
Eddie Hung	7c92b6852f	abc9_ops: sort LUT delays to be ascending	2020-02-27 10:17:29 -08:00
Eddie Hung	fb60d82971	ice40: move over to specify blocks for -abc9	2020-02-27 10:17:29 -08:00
Eddie Hung	a85c55113f	synth_ecp5: use +/abc9_model.v	2020-02-27 10:17:29 -08:00
Eddie Hung	8408c13405	Update xilinx for ABC9	2020-02-27 10:17:29 -08:00
Eddie Hung	ac24a23e31	Create +/abc9_model.v for $__ABC9_{DELAY,FF_}	2020-02-27 10:17:29 -08:00
Eddie Hung	7317521c6f	abc9_ops: output LUT area	2020-02-27 10:17:29 -08:00
Eddie Hung	d2284715fa	ecp5: remove small LUT entries	2020-02-27 10:17:29 -08:00
Eddie Hung	0ed550d83c	abc9_ops: cope with T_LIMIT{,2}_{MIN,TYP,MAX} and auto-gen small LUTs	2020-02-27 10:17:29 -08:00
Eddie Hung	ccc84f8923	Fix commented out specify statement	2020-02-27 10:17:29 -08:00
Eddie Hung	12d70ca8fb	xilinx: improve specify functionality	2020-02-27 10:17:29 -08:00
Eddie Hung	46a89d7264	ecp5: deprecate abc9_{arrival,required} and *.{lut,box}	2020-02-27 10:17:29 -08:00
Eddie Hung	577545488a	xilinx: use specify blocks in place of abc9_{arrival,required}	2020-02-27 10:17:29 -08:00
Eddie Hung	0e7c55e2a7	Auto-generate .box/.lut files from specify blocks	2020-02-27 10:17:29 -08:00