mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-09 23:53:26 +00:00
Code Activity
12767 commits 111 branches 55 tags 45 MiB
Commit graph

1 commit

Author SHA1 Message Date
N. Engelhardt
e230a871be synth_quicklogic: rearrange files to prepare for adding more architectures 2023-11-27 08:37:33 +01:00
Renamed from techlibs/quicklogic/cells_sim.v (Browse further)