16 commits

Author	SHA1	Message	Date
Clifford Wolf	4b8200eb49	Fixed segfault on invalid verilog constant 1'b_	2015-09-22 08:13:09 +02:00
Clifford Wolf	a7ab9172f9	Small corrections to const2ast warning messages	2015-08-17 16:22:53 +02:00
Florian Zeitz	0491042849	Check base-n literals only contain valid digits	2015-08-17 15:37:33 +02:00
Florian Zeitz	64ccbf8510	Warn on literals exceeding the specified bit width	2015-08-17 15:27:35 +02:00
Larry Doolittle	6c00704a5e	Another block of spelling fixes ... Smaller this time	2015-08-14 23:27:05 +02:00
Clifford Wolf	45ee2ba3b8	Fixed handling of [a-fxz?] in decimal constants	2015-08-11 11:32:37 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Clifford Wolf	56c7d1e266	Fixed two minor bugs in constant parsing	2014-11-24 14:39:24 +01:00
Clifford Wolf	87333f3ae2	Added warning for use of 'z' constants in HDL	2014-11-14 19:59:50 +01:00
Clifford Wolf	1cb25c05b3	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	2014-07-31 13:19:47 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	7f57bc8385	Improved parsing of large integer constants	2014-06-15 08:48:17 +02:00
Clifford Wolf	0b47d907d3	Fixed handling of unsized constants in verilog frontend	2014-01-24 15:05:24 +01:00
Clifford Wolf	00a6c1d9a5	Major redesign of expr width/sign detecion (verilog/ast frontend)	2013-07-09 14:31:57 +02:00
Clifford Wolf	46fbe9d262	Added SAT generator and simple sat_solve command	2013-06-07 13:59:13 +02:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00