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Code Activity
6377 commits 121 branches 59 tags 72 MiB
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Author SHA1 Message Date
Eddie Hung
0eb7150a57 Add test 2019-04-25 18:08:05 -07:00
Eddie Hung
af3c374a35 Elaborate on help message 2019-04-25 17:35:39 -07:00
Eddie Hung
3042d58330 Merge branch 'eddie/split_shiftx' into xc7mux 2019-04-25 17:31:27 -07:00
Eddie Hung
ccd0729456 Add split_shiftx command 2019-04-25 17:23:59 -07:00
Eddie Hung
8d00b9ef7e Make pmgen support files more generic 2019-04-25 17:23:46 -07:00
Eddie Hung
feff976454 synth_xilinx to call bitblast_shiftx 2019-04-25 17:11:18 -07:00
Eddie Hung
408161ea3a
Misspelling 2019-04-25 16:46:13 -07:00
Eddie Hung
eec314e262 Remove topo sort no-loop assertion, with test 2019-04-24 21:06:53 -07:00
Eddie Hung
f96d82a5f1 Add -nocarry option to synth_xilinx 2019-04-24 16:46:41 -07:00
Eddie Hung
ac2aff9e28 Fix abc9 with (* keep *) wires 2019-04-23 16:11:39 -07:00
Eddie Hung
bfd71e0990 Fix abc9 with (* keep *) wires 2019-04-23 16:11:14 -07:00
Eddie Hung
9d122d3c51 Refactor into AigerReader::post_process() 2019-04-23 15:06:19 -07:00
Clifford Wolf
67005633e2 Add specify support to README 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 23:01:38 +02:00
Clifford Wolf
64925b4e8f Improve $specrule interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 22:57:10 +02:00
Eddie Hung
d9c915042a Move clean from aigerparse to abc9 2019-04-23 13:42:35 -07:00
Eddie Hung
91c3afcab7 Use nonblocking 2019-04-23 13:42:06 -07:00
Clifford Wolf
4575e4ad86 Improve $specrule interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 22:18:04 +02:00
Clifford Wolf
71c38d9de5 Add $specrule cells for $setup/$hold/$skew specify rules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
634482380c Preserve $specify[23] cells 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
012c6af088 Allow $specify[23] cells in blackbox modules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
e807e88b60 Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
846eb5ea98 Add $specify2/$specify3 support to write_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
0bf9d0087c Add support for $assert/$assume/$cover to write_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
aec2475a9d Add CellTypes support for $specify2 and $specify3 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
e1d73e03d3 Add InternalCellChecker support for $specify2 and $specify3 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
b232e027bf Checking and fixing specify cells in genRTLIL 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
41b843c27b Un-break default specify parser 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
3cc95fb4be Add specify parser 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
a7e11261bd Add $specify2 and $specify3 cells to simlib 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
b2020ab44f
Merge pull request #957 from YosysHQ/oai4fix 
Fixes for OAI4 cell implementation
 2019-04-23 19:59:39 +02:00
David Shah
742c2f245d Fixes for OAI4 cell implementation 
Fixes #955 and the underlying issue in #954

Signed-off-by: David Shah <dave@ds0.me>
 2019-04-23 17:54:00 +01:00
Eddie Hung
c6156f3118
Format some names using inline code 2019-04-23 09:01:10 -07:00
Eddie Hung
f66792c43a
Fix spelling 2019-04-23 08:58:34 -07:00
Clifford Wolf
c84cdc711c Remove some left-over log_dump() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 17:55:41 +02:00
Eddie Hung
4df4a97ffa Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig 2019-04-22 18:20:39 -07:00
Eddie Hung
0bd2bfa737 Merge remote-tracking branch 'origin/master' into xaig 2019-04-22 18:15:28 -07:00
Eddie Hung
60026842b2 Tweak 2019-04-22 17:59:56 -07:00
Eddie Hung
26e461f47d Fix for A_WIDTH == 2 but B_WIDTH==3 2019-04-22 17:58:28 -07:00
Eddie Hung
5f30a8795d Tidy up 2019-04-22 17:47:05 -07:00
Eddie Hung
8f30019b68 Revert "Temporarily remove 'r' extension" 
This reverts commit eaf3c24772.
 2019-04-22 17:41:21 -07:00
Eddie Hung
1fa2c36fbd Trim A_WIDTH by Y_WIDTH-1 2019-04-22 17:14:11 -07:00
Eddie Hung
69863f7698 Add comment 2019-04-22 16:58:44 -07:00
Eddie Hung
61161faefc Fix for mux_case_* mappings 2019-04-22 16:56:18 -07:00
Eddie Hung
ac1e13819e Fix for non-pow2 width muxes 2019-04-22 14:26:13 -07:00
Eddie Hung
d9daf09cf3
Merge pull request #914 from YosysHQ/xc7srl 
synth_xilinx to now infer SRL16E/SRLC32E
 2019-04-22 13:31:30 -07:00
Eddie Hung
75b96b1aff Add synth_xilinx -nomux option 2019-04-22 12:36:15 -07:00
Eddie Hung
79fb291dbe Cleanup, call pmux2shiftx even without -nosrl 2019-04-22 12:14:37 -07:00
Eddie Hung
4cfef7897f Merge branch 'xaig' into xc7mux 2019-04-22 11:58:59 -07:00
Eddie Hung
eaf3c24772 Temporarily remove 'r' extension 2019-04-22 11:54:19 -07:00
Eddie Hung
4486a98fd5 Merge remote-tracking branch 'origin/xc7srl' into xc7mux 2019-04-22 11:45:49 -07:00