282 commits

Author	SHA1	Message	Date
Clifford Wolf	e9fe57c75e	Only allow posedge/negedge with 1 bit wide signals	2016-08-10 19:32:11 +02:00
Clifford Wolf	4056312987	Added $anyconst and $aconst	2016-07-27 15:41:22 +02:00
Clifford Wolf	d7763634b6	After reading the SV spec, using non-standard predict() instead of expect()	2016-07-21 13:34:33 +02:00
Clifford Wolf	721f1f5ecf	Added basic support for $expect cells	2016-07-13 16:56:17 +02:00
Ruben Undheim	178ff3e7f6	Added support for SystemVerilog packages with localparam definitions	2016-06-18 10:53:55 +02:00
Clifford Wolf	766032c5f8	Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}	2016-05-27 17:55:03 +02:00
Clifford Wolf	e9ceec26ff	fixed typos in error messages	2016-05-27 16:37:36 +02:00
Clifford Wolf	5a09fa4553	Fixed handling of parameters and const functions in casex/casez pattern	2016-04-21 15:31:54 +02:00
Clifford Wolf	bcc873b805	Fixed some visual studio warnings	2016-02-13 17:31:24 +01:00
Rick Altherr	34969d4140	genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSignalFromCaseTree()	2016-01-31 09:20:16 -08:00
Clifford Wolf	34f2b84fb6	Fixed handling of parameters and localparams in functions	2015-11-11 10:54:35 +01:00
Clifford Wolf	207736b4ee	Import more std:: stuff into Yosys namespace	2015-10-25 19:30:49 +01:00
Clifford Wolf	924d9d6e86	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
Clifford Wolf	84bf862f7c	Spell check (by Larry Doolittle)	2015-08-14 10:56:05 +02:00
Clifford Wolf	8d6d5c30d9	Added WORDS parameter to $meminit	2015-07-31 10:40:09 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Clifford Wolf	422794c584	Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()	2015-03-01 11:20:22 +01:00
Clifford Wolf	1f1deda888	Added non-std verilog assume() statement	2015-02-26 18:47:39 +01:00
Clifford Wolf	c2ba4fb2fd	Convert floating point cell parameters to strings	2015-02-18 23:35:23 +01:00
Clifford Wolf	e9368a1d7e	Various fixes for memories with offsets	2015-02-14 14:21:15 +01:00
Clifford Wolf	a8e9d37c14	Creating $meminit cells in verilog front-end	2015-02-14 10:49:30 +01:00
Clifford Wolf	234a45a3d5	Ignore explicit assignments to constants in HDL code	2015-02-08 00:58:03 +01:00
Clifford Wolf	c8305e3a6d	Fixed a bug with autowire bit size ... (removed leftover from when we tried to auto-size the wires)	2015-02-08 00:48:23 +01:00
Clifford Wolf	eefe78be09	Fixed memory->start_offset handling	2015-01-01 12:56:01 +01:00
Clifford Wolf	137f35373f	Changed more code to dict<> and pool<>	2014-12-28 19:24:24 +01:00
Clifford Wolf	edb3c9d0c4	Renamed extend() to extend_xx(), changed most users to extend_u0()	2014-12-24 09:51:17 +01:00
Clifford Wolf	fe829bdbdc	Added log_warning() API	2014-11-09 10:44:23 +01:00
Clifford Wolf	4569a747f8	Renamed SIZE() to GetSize() because of name collision on Win32	2014-10-10 17:07:24 +02:00
Clifford Wolf	deff416ea7	Fixed assignment of out-of bounds array element	2014-09-06 17:58:27 +02:00
Clifford Wolf	8927aa6148	Removed $bu0 cell type	2014-09-04 02:07:52 +02:00
Clifford Wolf	7bfc4ae120	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	2014-08-21 12:43:51 +02:00
Clifford Wolf	64713647a9	Improved AST ProcessGenerator performance	2014-08-17 02:17:49 +02:00
Clifford Wolf	d491fd8c19	Use stackmap<> in AST ProcessGenerator	2014-08-17 00:57:24 +02:00
Clifford Wolf	83e2698e10	AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map	2014-08-16 19:31:59 +02:00
Clifford Wolf	978a933b6a	Added RTLIL::SigSpec::to_sigbit_map()	2014-08-14 23:14:47 +02:00
Clifford Wolf	c83b990458	Changed the AST genWidthRTLIL subst interface to use a std::map	2014-08-14 23:02:07 +02:00
Clifford Wolf	b9bd22b8c8	More cleanups related to RTLIL::IdString usage	2014-08-02 13:19:57 +02:00
Clifford Wolf	cdae8abe16	Renamed port access function on RTLIL::Cell, added param access functions	2014-07-31 16:38:54 +02:00
Clifford Wolf	1cb25c05b3	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	2014-07-31 13:19:47 +02:00
Clifford Wolf	397b00252d	Added $shift and $shiftx cell types (needed for correct part select behavior)	2014-07-29 16:35:13 +02:00
Clifford Wolf	48822e79a3	Removed left over debug code	2014-07-28 19:38:30 +02:00
Clifford Wolf	ec58965967	Fixed part selects of parameters	2014-07-28 19:24:28 +02:00
Clifford Wolf	a03297a7df	Set results of out-of-bounds static bit/part select to undef	2014-07-28 16:09:50 +02:00
Clifford Wolf	55521c085a	Fixed RTLIL code generator for part select of parameter	2014-07-28 15:31:19 +02:00
Clifford Wolf	0598bc8708	Fixed width detection for part selects	2014-07-28 15:19:34 +02:00
Clifford Wolf	27a872d1e7	Added support for "upto" wires to Verilog front- and back-end	2014-07-28 14:25:03 +02:00
Clifford Wolf	3c45277ee0	Added wire->upto flag for signals such as "wire [0:7] x;"	2014-07-28 12:12:13 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	ee65dea738	Fixed signdness detection of expressions with bit- and part-selects	2014-07-28 10:10:08 +02:00
Clifford Wolf	f9946232ad	Refactoring: Renamed RTLIL::Module::wires to wires_	2014-07-27 01:49:51 +02:00