mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-10 19:27:07 +00:00
Code Activity
10775 commits 96 branches 53 tags 64 MiB
Commit graph

3 commits

Author SHA1 Message Date
Marcelina Kościelnicka 192601385f rtlil: Fix process memwr roundtrip. 
Fixes #2646 fallout.
 2021-03-23 19:49:47 +01:00
Marcelina Kościelnicka 4e03865d5b Add support for memory writes in processes. 2021-03-08 20:16:29 +01:00
whitequark 00e7dec7f5 Replace "ILANG" with "RTLIL" everywhere. 
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.

Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
 2020-08-26 17:29:32 +00:00