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Author SHA1 Message Date
Eddie Hung
cba3073026 submod to bitty rather bussy, for bussy wires used as input and output 2019-11-22 20:53:58 -08:00
Eddie Hung
08f85e6438 Stray dump 2019-11-22 20:53:48 -08:00
Eddie Hung
8119383f81 Constant driven signals are also an input to submodules 2019-11-22 17:23:51 -08:00
Eddie Hung
4fdcf8f7d7 Add another test with constant driver 2019-11-22 17:23:34 -08:00
Eddie Hung
573396851a Oops 2019-11-22 17:03:30 -08:00
Eddie Hung
8779faf789 Cleanup spacing 2019-11-22 16:50:09 -08:00
Eddie Hung
6a52897aee sigmap(wire) should inherit port_output status of POs 2019-11-22 16:48:11 -08:00
Eddie Hung
2ef2e2c040 Add testcase 2019-11-22 16:48:11 -08:00
Clifford Wolf
c03b6a3e9c
Merge pull request #1517 from YosysHQ/clifford/optmem 
Add "opt_mem" pass
 2019-11-22 18:11:58 +01:00
Clifford Wolf
caa3b21f8b
Merge pull request #1515 from YosysHQ/clifford/svastuff 
Add Verific/SVA support for "always" and "nexttime" properties
 2019-11-22 18:10:34 +01:00
Clifford Wolf
03fb92ed6f Add "opt_mem" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-22 17:45:22 +01:00
Clifford Wolf
db323685a4 Add Verific support for SVA nexttime properties 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-22 16:11:56 +01:00
Clifford Wolf
e93e4a7a2c Improve handling of verific primitives in "verific -import -V" mode 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-22 16:00:07 +01:00
Clifford Wolf
6af0d03fae Add Verific SVA support for "always" properties 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-22 15:52:21 +01:00
Clifford Wolf
72d2ef6fd0
Merge pull request #1511 from YosysHQ/dave/always 
sv: Error checking for always_comb, always_latch and always_ff
 2019-11-22 15:32:29 +01:00
Marcin Kościelnicki
e110df9c48 gowin: Remove show command from tests. 2019-11-22 14:49:35 +01:00
Marcin Kościelnicki
1d098b7195 gowin: Add missing .gitignore entries 2019-11-22 14:40:36 +01:00
David Shah
b60f32c6ec Update CHANGELOG and README 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-22 12:46:19 +00:00
David Shah
49b670ca38 sv: Add tests for SV always types 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-21 21:06:28 +00:00
David Shah
ca99b1ee8d proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-21 20:46:41 +00:00
David Shah
9e4801cca7 sv: Correct parsing of always_comb, always_ff and always_latch 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-21 20:27:19 +00:00
Clifford Wolf
0ac330bb81
Merge pull request #1507 from YosysHQ/clifford/verificfixes 
Some fixes in our Verific integration
 2019-11-20 13:49:27 +01:00
Clifford Wolf
55bda2b2c6 Correctly treat empty modules as blackboxes in Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-20 12:56:31 +01:00
Clifford Wolf
f6ff311a1d Do not rename VHDL entities to "entity(impl)" when they are top modules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-20 12:54:10 +01:00
Clifford Wolf
7ea0a5937b
Merge pull request #1449 from pepijndevos/gowin 
Improvements for gowin support
 2019-11-19 17:29:27 +01:00
Pepijn de Vos
8ab412eb16 Remove dff init altogether 
The hardware does not actually support it.
In reality it is always initialised to its reset value.
 2019-11-19 15:53:44 +01:00
Marcin Kościelnicki
15232a48af Fix #1462, #1480. 2019-11-19 08:57:39 +01:00
Marcin Kościelnicki
7a9081440c xilinx: Add simulation models for MULT18X18* and DSP48A*. 
This adds simulation models for the following primitives:

- MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3)
- MULT18X18SIO (Spartan 3E, Spartan 3A)
- DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1
- DSP48A1 (Spartan 6)
 2019-11-19 01:00:58 +01:00
Pepijn de Vos
dd8c7e1ddd add help for nowidelut and abc9 options 2019-11-18 14:26:09 +01:00
Clifford Wolf
9ee3c57e46
Merge pull request #1497 from YosysHQ/mwk/extract-fa-fix 
Fix #1496.
 2019-11-18 10:53:14 +01:00
whitequark
cdb566b2d6
Merge pull request #1494 from whitequark/write_verilog-extmem 
write_verilog: add -extmem option, to write split memory init files
 2019-11-18 09:37:14 +00:00
Marcin Kościelnicki
38e72d6e13 Fix #1496. 2019-11-18 04:16:48 +01:00
whitequark
3c643c57df write_verilog: add -extmem option, to write split memory init files. 
Some toolchains (in particular Quartus) are pathologically slow if
a large amount of assignments in `initial` blocks are used.
 2019-11-18 01:27:21 +00:00
Clifford Wolf
527434de49
Merge pull request #1492 from YosysHQ/dave/wreduce-fix-arst 
wreduce: Don't trim zeros or sext when not matching ARST_VALUE
 2019-11-17 10:42:30 +01:00
Pepijn de Vos
32f0296df1 Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin 2019-11-16 12:43:17 +01:00
David Shah
51e4e29bb1 ecp5: Use new autoname pass for better cell/net names 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-15 21:03:11 +00:00
David Shah
f5804a84fd wreduce: Don't trim zeros or sext when not matching ARST_VALUE 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-14 18:43:15 +00:00
Clifford Wolf
e907ee4fde
Merge pull request #1490 from YosysHQ/clifford/autoname 
Add "autoname" pass and use it in "synth_ice40"
 2019-11-14 18:03:44 +01:00
Clifford Wolf
4b18a4528b
Merge pull request #1444 from btut/feature/python_wrappers/globals_and_streams 
Python Wrappers: Expose global variables and allow logging to python streams
 2019-11-14 12:10:12 +01:00
Clifford Wolf
056ef76711
Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim 
ice40: Support for post-place-and-route timing simulations
 2019-11-14 12:07:25 +01:00
Clifford Wolf
f453f579bf Merge branch 'makaimann-label-bads-btor' 2019-11-14 11:57:53 +01:00
Clifford Wolf
cd44826d50 Use cell name for btor bad state props when it is a public name 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-14 11:57:38 +01:00
Clifford Wolf
89834b98f7 Merge branch 'label-bads-btor' of https://github.com/makaimann/yosys into makaimann-label-bads-btor 2019-11-14 11:52:41 +01:00
Clifford Wolf
07c854b7af Add "autoname" pass and use it in "synth_ice40" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-13 13:41:16 +01:00
whitequark
ab0fb19cff
Merge pull request #1488 from whitequark/flowmap-fixes 
flowmap: fix a few crashes
 2019-11-13 11:57:17 +00:00
Clifford Wolf
6e332161db
Merge pull request #1486 from YosysHQ/clifford/fsmdetectfix 
Bugfix in fsm_detect
 2019-11-13 12:34:27 +01:00
Clifford Wolf
4be5a0fd7c Update fsm_detect bugfix 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-12 17:31:30 +01:00
Clifford Wolf
16df8f5a32 Bugfix in fsm_detect 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-12 14:26:02 +01:00
Clifford Wolf
e0ba78bdf2
Merge pull request #1484 from YosysHQ/clifford/cmp2luteqne 
Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp
 2019-11-12 10:24:12 +01:00
Makai Mann
d88cc139a0 Add an info string symbol for bad states in btor backend 2019-11-11 16:40:51 -08:00