mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-12-25 21:46:52 +00:00
Code Activity
16223 commits 114 branches 62 tags 60 MiB
Commit graph

5 commits

Author SHA1 Message Date
Lofty
8fad004fb8 synth_analogdevices: update timing model and tests 2025-11-12 22:44:12 +00:00
Krystine Sherwin
d7248303c6 analogdevices: Extra tests 
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
 2025-11-12 22:44:12 +00:00
Lofty
e189ee10aa analogdevices: DSP inference 2025-11-12 22:44:12 +00:00
Krystine Sherwin
3cf01c399a analogdevices: Update lutram.ys test 2025-11-12 22:44:12 +00:00
Lofty
8651e3ac89 test suite 2025-11-12 22:44:11 +00:00