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10533 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Alberto Gonzalez
4ccaf048a5
Simplify passes/techmap/abc.cc and remove superfluous RTLIL::SigSpec constructions. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-04-14 02:39:44 +00:00
Eddie Hung
0808318d55 xaiger: add check for $__ABC9_DELAY model 2020-04-13 19:11:23 -07:00
Eddie Hung
f44b287f8e
Merge pull request #1568 from YosysHQ/eddie/fix_zinit 
zinit: fixes for $_DFF_[NP][NP][01]_and $adff cells with init = 1'b1
 2020-04-13 18:33:42 -07:00
Alberto Gonzalez
c479fdeb85
Add dict support for rvalue references and C++11 move semantics. 2020-04-13 23:52:16 +00:00
Eddie Hung
b75c5bf743 zinit: resolve one more comment by @mwkmwkmwk 2020-04-13 15:25:37 -07:00
Eddie Hung
c6afce7638 zinit: fix review comments from @mwkmwkmwk 2020-04-13 15:16:51 -07:00
Eddie Hung
091297b9ee tests: zinit on $adff 2020-04-13 14:29:44 -07:00
Eddie Hung
70bca35f9c zinit: operate on $adff, erase (* init *) entries on consumption 2020-04-13 14:28:53 -07:00
Eddie Hung
1cdfdbc6d1 Fix S/R comment; thanks @mwkmwkmwk 2020-04-13 13:45:18 -07:00
Eddie Hung
4617aa8ccd zinit to transform set/reset value of $_DFF_[NP][NP][01]_ 2020-04-13 13:45:18 -07:00
Eddie Hung
3c5a9411b1 Add testcase for $_DFF_[NP][NP][01]_ 2020-04-13 13:16:49 -07:00
Eddie Hung
b97a9cd3f3 Supress error for unhandled \init if whole module selected 2020-04-13 13:16:49 -07:00
Marcelina Kościelnicka
840bb17089 opt_expr: Optimize multiplications with low 0 bits in operands. 
Fixes #1500.
 2020-04-13 16:52:22 +02:00
whitequark
5448f9c85d
Merge pull request #1910 from boqwxp/cleanup_ilang_parser 
Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
 2020-04-13 08:40:45 +00:00
Alberto Gonzalez
8a84674a42
Clean up pseudo-private member usage in frontends/ilang/ilang_parser.y. 2020-04-13 04:22:00 +00:00
Xiretza
7f1d83c5db Add .gitignore to tests/select/ 2020-04-12 22:45:45 +02:00
David Shah
87555c44d5
Merge pull request #1907 from YosysHQ/dave/fix-1906 
verilog: Fix write to deleted object
 2020-04-12 21:08:02 +01:00
David Shah
0a178de1b3 verilog: Fix write to deleted object 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-12 18:49:09 +01:00
Xiretza
333981acfd
Suppress output of Makefile.conf when printing source versions 
The make targets echo-yosys-ver, echo-git-ver and echo-abc-rev can be
used to programmatically extract contents of make variables for external
scripts. Unfortunately, when a Makefile.conf exists, its contents would
also be echoed, making the output almost unusable. This patch
selectively disables this functionality for these special targets.
 2020-04-11 13:23:08 +02:00
Alberto Gonzalez
e300766fb3
Use pool instead of std::set. 2020-04-11 09:41:09 +00:00
Alberto Gonzalez
73bd7fb01d
Use dict instead of std::map. 2020-04-11 06:53:59 +00:00
David Shah
85672a6c1f memory_bram: Fix ignorance of valid, matched rules 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-10 21:48:04 +01:00
whitequark
93ef516d91
Merge pull request #1603 from whitequark/ice40-ram_style 
ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
 2020-04-10 14:51:01 +00:00
Miodrag Milanović
93c6c67798
Merge pull request #1893 from mmicko/program_prefix 
Support custom PROGRAM_PREFIX
 2020-04-10 16:33:01 +02:00
Miodrag Milanovic
af7b7b6dc1 Keep libyosys name same as befire, but put it in directory 2020-04-10 15:02:48 +02:00
Miodrag Milanovic
0d789c5a3b Support custom PROGRAM_PREFIX 2020-04-10 10:38:40 +02:00
whitequark
7c06cb6157
Merge pull request #1562 from whitequark/write_cxxrtl 
write_cxxrtl: new backend
 2020-04-10 01:24:31 +00:00
Eddie Hung
371af7da38
Merge pull request #1858 from YosysHQ/eddie/fix1856 
kernel: include "kernel/constids.inc"
 2020-04-09 14:23:47 -07:00
Sahand Kashani
959a00a46f Fix indentation 2020-04-09 21:16:02 +02:00
Eddie Hung
f11dd6e208 tests: add a quick plugin test 2020-04-09 09:45:20 -07:00
Eddie Hung
60ffc21e64 kernel: include "kernel/constids.inc" instead of "constids.inc" 2020-04-09 09:14:03 -07:00
Marcelina Kościelnicka
516857f3ba [NFCI] Deduplicate builtin FF cell types list 
A few passes included the same list of FF cell types.  Make it a global
const instead.

The zinit pass also seems to include a list like that, but given that
it seems to be completely broken at the time (see #1568 discussion),
I'm going to pretend I didn't see that.
 2020-04-09 18:05:06 +02:00
N. Engelhardt
7f33d43e3b
Merge pull request #1890 from boqwxp/cleanup_memory_collect 
Clean up `passes/memory/memory_collect.cc`.
 2020-04-09 14:01:29 +02:00
N. Engelhardt
ed738b8ddb
Merge pull request #1889 from boqwxp/cleanup_memory_unpack 
Clean up `passes/memory/memory_unpack.cc`.
 2020-04-09 14:00:44 +02:00
N. Engelhardt
14d24bc589
Merge pull request #1887 from boqwxp/cleanup_hilomap 
Clean up `passes/techmap/hilomap.cc`.
 2020-04-09 12:09:44 +02:00
Alberto Gonzalez
de5e6fa56a
Clean up passes/sat/qbfsat.cc. 
Makes various cosmetic fixes, removes superfluous `hasPort()` check, and uses `emplace_back()` instead of `push_back()`.
 2020-04-09 07:47:44 +00:00
Alberto Gonzalez
652050b273
Clean up passes/memory/memory_collect.cc. 2020-04-09 05:43:05 +00:00
Alberto Gonzalez
685dc37d27
Clean up passes/memory/memory_unpack.cc. 2020-04-09 05:38:36 +00:00
Alberto Gonzalez
83222193af
Clean up passes/techmap/hilomap.cc. 2020-04-09 05:28:32 +00:00
whitequark
4737f426ff write_cxxrtl: add basic documentation. 2020-04-09 04:08:36 +00:00
whitequark
753e34007d write_cxxrtl: add support for $dlatch and $dlatchsr cells. 
Also, fix codegen for $dffe and $adff.
 2020-04-09 04:08:36 +00:00
whitequark
711df56ad0 write_cxxrtl: add support for $sr cell. 
Also, fix the semantics of SET/CLR inputs of the $dffsr cell, and
fix the scheduling of async FF cells to consider ARST/SET/CLR->Q
as a forward combinatorial arc.
 2020-04-09 04:08:36 +00:00
whitequark
9534b51277 write_cxxrtl: add support for $slice and $concat cells. 2020-04-09 04:08:36 +00:00
whitequark
01e6850bd3 write_cxxrtl: improve writable memory handling. 
This commit reduces space and time overhead for writable memories
to O(write port count) in both cases; implements handling for write
port priorities; and simplifies runtime representation of memories.
 2020-04-09 04:08:36 +00:00
whitequark
fb0270b752 write_cxxrtl: add support for hierarchical designs. 
Hierarchical design simulations are generally much slower, but this
comes with a major increase in flexibility:
 1. Since the `flatten` pass currently does not support flattening
    of designs with processes, this is the only way to simulate such
    designs with cxxrtl.
 2. Support for hierarchy paves way for simulation black boxes,
    which are necessary for e.g. replacing PHYs with C++ code that
    integrates with the host system.
 2020-04-09 04:08:36 +00:00
whitequark
3376dcf37c write_cxxrtl: avoid undefined behavior on out-of-bounds memory access. 
After this commit, if NDEBUG is not defined, out-of-bounds accesses
cause assertion failures for reads and writes. If NDEBUG is defined,
out-of-bounds reads return zeroes, and out-of-bounds writes are
ignored.

This commit also adds support for memories that start with a non-zero
index (`Memory::start_offset` in RTLIL).
 2020-04-09 04:08:36 +00:00
whitequark
5157691f0e write_cxxrtl: statically schedule comb logic and localize wires. 
This results in further massive gains in performance, modest decrease
in compile time, and, for designs without feedback arcs, makes it
possible to run eval() once per clock edge in certain conditions.
 2020-04-09 04:08:36 +00:00
whitequark
d6d7273421 write_cxxrtl: elide wires for results of comb cells used once. 
This results in massive gains in performance, equally massive
reduction in compile time, and improved readability.
 2020-04-09 04:08:36 +00:00
whitequark
d20e971725 write_cxxrtl: new backend. 
This commit adds a basic implementation that isn't very performant
but implements most of the planned features.
 2020-04-09 04:08:36 +00:00
whitequark
42e7e44207
Merge pull request #1857 from whitequark/splitnets-skip-processes 
splitnets: skip modules with processes
 2020-04-09 04:03:30 +00:00